公开(公告)号：US20220139484A1

公开(公告)日：2022-05-05

申请号：US17353583

申请日：2021-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinyoung Kim ,  Sehwan Park ,  Youngdeok Seo ,  Ilhan Park

IPC: G11C29/42 ,  G11C29/44 ,  G11C16/34 ,  G11C16/04 ,  G11C16/26 ,  G11C16/08 ,  G11C16/24

Abstract: A nonvolatile memory device includes a plurality of memory blocks and a control logic circuit configured to perform a first page on-chip valley search (OVS) operation on memory cells connected to one wordline of a memory block selected in response to an address, among the plurality of memory blocks, in response to a first read command. The control logic circuit is further configured to change a read level of at least one state using detection information of the first page OVS operation, and to perform a second page read operation on the memory cells using the changed read level in response to a second read command.

公开(公告)号：US20220139475A1

公开(公告)日：2022-05-05

申请号：US17328487

申请日：2021-05-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngdeok SEO ,  Jinyoung Kim ,  Sehwan Park ,  Dongmin Shin

IPC: G11C16/34 ,  G11C16/26 ,  G11C16/10 ,  G11C16/08 ,  G06K9/62 ,  G06N20/10

Abstract: A non-volatile memory device includes a memory cell array including memory cells, a page buffer circuit including page buffers respectively connected to bit lines, a buffer memory, and a control logic configured to control a read operation on the memory cells. In the read operation, the control logic obtains valley search detection information including read target block information and word line information by performing a valley search sensing operation on a distribution of threshold voltages of the memory cells, obtains a plurality of read levels using a read information model by inputting the valley search detection information into the read information model, and performs a main sensing operation for the read operation.

公开(公告)号：US11315631B2

公开(公告)日：2022-04-26

申请号：US17021409

申请日：2020-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Makoto Hirano ,  Jinyoung Kim

IPC: G11C11/00 ,  G11C13/00

Abstract: A three-dimensional (3D) memory device includes a memory cell array, a first sense amplifier and a second sense amplifier. The memory cell array includes lower memory cells respectively arranged in regions where lower word lines intersect with bit lines and upper memory cells respectively arranged in regions where upper word lines intersect with the bit lines. The first sense amplifier is connected to a first lower word line and performs a data sensing operation on a first lower memory cell connected between a first bit line and the first lower word line. The second sense amplifier is connected to a first upper word line and performs a data sensing operation on a first upper memory cell connected between the first bit line and the first upper word line. The data sensing operations of the first and second sense amplifiers are performed in parallel.

公开(公告)号：US20220028478A1

公开(公告)日：2022-01-27

申请号：US17147851

申请日：2021-01-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sehwan PARK ,  Jinyoung Kim ,  Ilhan Park ,  Kyoman Kang ,  Sangwan Nam

IPC: G11C29/50 ,  G11C29/44 ,  G11C7/10 ,  G11C8/18

Abstract: A non-volatile memory device includes a memory cell array including a plurality of memory blocks that includes a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a row decoder configured to select one among the plurality of memory blocks, based on an address, a voltage generator configured to apply word line voltages corresponding to selected word lines and unselected word lines, among the plurality of word lines, page buffers connected to the plurality of bit lines and configured to read data from a memory cell connected to one among the selected word lines of the selected one among the plurality of memory blocks, and a control logic configured to control the row decoder, the voltage generator, and the page buffers.

公开(公告)号：US11152779B2

公开(公告)日：2021-10-19

申请号：US16427652

申请日：2019-05-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daun Jung ,  Min Lee ,  Jinyoung Kim ,  Jongkwang Jung

IPC: H02H5/00 ,  H02H1/00 ,  H04R3/00

Abstract: The disclosure provides a technique to prevent and/or reduce a terminal of an audio jack from being corroded due to residual moisture introduced into the audio jack. According to various embodiments of the disclosure, an electronic device may include an audio jack including a plurality of terminals including a first detection terminal and a second detection terminal; at least one processor functionally connected to the audio jack; and a memory. The memory may store instructions that, when executed by the at least one processor, control the electronic device to: detect an occurrence of an insertion interrupt of an object in the audio jack through the first detection terminal, determine whether the object is a jack plug based on an impedance value measured through the second detection terminal, and stop applying a voltage to the first detection terminal when the object is determined not to be the jack plug.

公开(公告)号：US20250151441A1

公开(公告)日：2025-05-08

申请号：US18809676

申请日：2024-08-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changkyu Lee ,  Jinyoung Kim ,  Byoungho Kwon ,  Dhami Park ,  Jihun Lim

IPC: H01L27/146

Abstract: An image sensor includes a substrate, a first pixel disposed in the substrate, the first pixel including a first photoelectric conversion region, a second pixel disposed adjacent to the first pixel in the substrate, the second pixel including a second photoelectric conversion region, a first floating diffusion region in the first pixel, a second floating diffusion region in the second pixel, an insulation layer on the substrate, and a first buried connect penetrating the insulation layer and connected to the first floating diffusion region and the second floating diffusion region, wherein the first buried connect includes an upper surface and a lower surface, the upper surface of the first buried connect is at a higher vertical level than an upper surface of the insulation layer, and the lower surface of the first buried connect is at a higher or equal vertical level than a lower surface of the insulation layer.

公开(公告)号：US12266668B2

公开(公告)日：2025-04-01

申请号：US17643938

申请日：2021-12-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chongkwang Chang ,  Donghoon Khang ,  Jinyoung Kim ,  Kwangyoung Oh ,  Taehun Lee

IPC: H01L27/146

Abstract: An image sensor includes a substrate having first and second surfaces. A separation structure penetrates the substrate. Photoelectric conversion device regions are spaced apart from each other in the substrate. Color filters are disposed on the second surface of the substrate. Microlenses are disposed on the color filters. The separation structure includes lower and upper separation patterns, first line portions that run parallel to each other, and second line portions that perpendicularly intersect the first line portions. An upper surface of the lower separation pattern or a lower surface of the upper separation pattern has a wavy or sawtooth shape. In intersecting regions in which the first line portions and the second line portions intersect, a vertical length of one of the lower separation pattern and the upper separation pattern is about 2 to 10 times greater than a vertical length of the other.

公开(公告)号：US20250006770A1

公开(公告)日：2025-01-02

申请号：US18735325

申请日：2024-06-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihun Lim ,  Jinyoung Kim ,  Myunghae Seo ,  Sungki Min ,  Chang Kyu Lee

IPC: H01L27/146

Abstract: A dual vertical transfer gate, a transistor including the same, and a CMOS image sensing device including the same. In some embodiments, a gate of the dual vertical transfer transistor may include a pair of poles, which are extended to an n-type region of a photodiode, and a connecting portion, which connects the paired poles to each other. A first insulating pattern may be provided between the poles and on the substrate.

公开(公告)号：US20240020187A1

公开(公告)日：2024-01-18

申请号：US18374717

申请日：2023-09-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wandong KIM ,  Jinyoung Kim ,  Sehwan Park ,  Hyun Seo ,  Sangwan Nam

IPC: G06F11/07 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26

CPC classification number: G06F11/0727 ,  G06F11/0757 ,  G06F11/076 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C11/56

Abstract: An operating method of a nonvolatile memory device for programming multi-page data, the operating method including: receiving the multi-page data from a memory controller; programming first page data among the multi-page data to first memory cells connected to a word line adjacent to a selected word line; reading previous page data previously stored in second memory cells connected to the selected word line based on a first sensing value and a second sensing value after programming the first page data; calculating a first fail bit number by comparing first bits of the previous page data read based on the first sensing value to second bits of the previous page data read based on the second sensing value; and programming the previous page data read from the second memory cells and second page data among the multi-page data to the second memory cells based on the first fail bit number.

公开(公告)号：US11862273B2

公开(公告)日：2024-01-02

申请号：US18068337

申请日：2022-12-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sehwan Park ,  Jinyoung Kim ,  Youngdeok Seo ,  Dongmin Shin ,  Joonsuc Jang ,  Sungmin Joe

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/18 ,  G11C16/10 ,  G11C29/12 ,  G11C16/26

CPC classification number: G11C29/42 ,  G11C16/102 ,  G11C16/26 ,  G11C29/12015 ,  G11C29/18 ,  G11C29/4401 ,  G11C2029/1202 ,  G11C2029/1204 ,  G11C2029/1802

Abstract: A storage device includes a nonvolatile memory device and a memory controller to control the nonvolatile memory device. The nonvolatile memory device includes a memory cell array. The memory cell array includes a normal cell region, a parity cell region and a redundancy cell region. First bit-lines are connected to the normal cell region and the parity cell region and second bit-lines are connected to the redundancy cell region. The memory controller includes an error correction code (ECC) engine to generate parity data. The memory controller stores user data in the normal cell region, controls the nonvolatile memory device to perform a column repair on first defective bit-lines among the first bit-lines, assigns additional column addresses to the first defective bit-lines and the second bit-lines and stores at least a portion of the parity data in a region corresponding to the additionally assigned column addresses.