公开(公告)号：US09263257B2

公开(公告)日：2016-02-16

申请号：US14312707

申请日：2014-06-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chin-Cheng Chien ,  Hsin-Kuo Hsu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Chun-Yuan Wu

IPC: H01L21/205 ,  H01L21/336 ,  H01L21/8232 ,  H01L29/08 ,  H01L29/16 ,  H01L29/43 ,  H01L29/78 ,  H01L29/417 ,  H01L21/02 ,  H01L21/311 ,  H01L29/36 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L21/0228 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/31111 ,  H01L29/06 ,  H01L29/0657 ,  H01L29/1054 ,  H01L29/36 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7853

Abstract: A semiconductor device with fin-shaped structure is disclosed. The semiconductor device includes: a substrate; a fin-shaped structure on the substrate; and an epitaxial layer on a top surface and part of the sidewall of the fin-shaped structure, in which the epitaxial layer and the fin-shaped structure includes a linear gradient of germanium concentration therebetween.

Abstract translation: 公开了一种具有鳍状结构的半导体器件。 半导体器件包括：衬底; 基板上的鳍状结构; 以及在鳍状结构的顶表面和侧壁的一部分上的外延层，其中外延层和鳍状结构在其间包括锗浓度的线性梯度。

公开(公告)号：US20150380512A1

公开(公告)日：2015-12-31

申请号：US14848362

申请日：2015-09-09

Applicant: United Microelectronics Corp.

Inventor： Chan-Lon Yang ,  Chi-Mao Hsu ,  Chun-Yuan Wu ,  Tzyy-Ming Cheng ,  Shih-Fang Tzou ,  Chin-Fu Lin ,  Hsin-Fu Huang ,  Min-Chuan Tsai

IPC: H01L29/51 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L29/517 ,  H01L21/28088 ,  H01L29/165 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7843

Abstract: A method for manufacturing a metal gate structure includes providing a substrate having a high-K gate dielectric layer and a bottom barrier layer sequentially formed thereon, forming a work function metal layer on the substrate, and performing an anneal treatment to the work function metal layer in-situ.

Abstract translation: 一种金属栅极结构的制造方法，其特征在于，具备在其上依次形成有高K栅极电介质层和底部阻挡层的基板，在基板上形成功函数金属层，对功函数金属层进行退火处理 原位。

公开(公告)号：US09159831B2

公开(公告)日：2015-10-13

申请号：US13662561

申请日：2012-10-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Chien Liu ,  Chun-Yuan Wu ,  Chin-Fu Lin ,  Chin-Cheng Chien ,  Chia-Lin Hsu

IPC: H01L21/70 ,  H01L29/78 ,  H01L21/764 ,  H01L29/66 ,  H01L21/02 ,  H01L27/11

CPC classification number: H01L29/785 ,  H01L21/02225 ,  H01L21/764 ,  H01L27/11 ,  H01L29/66484 ,  H01L29/66795

Abstract: A multigate field effect transistor includes two fin-shaped structures and a dielectric layer. The fin-shaped structures are located on a substrate. The dielectric layer covers the substrate and the fin-shaped structures. At least two voids are located in the dielectric layer between the two fin-shaped structures. Moreover, the present invention also provides a multigate field effect transistor process for forming said multigate field effect transistor including the following steps. Two fin-shaped structures are formed on a substrate. A dielectric layer covers the substrate and the two fin-shaped structures, wherein at least two voids are formed in the dielectric layer between the two fin-shaped structures.

Abstract translation: 多栅场效应晶体管包括两个鳍状结构和介电层。 鳍状结构位于基底上。 电介质层覆盖基板和鳍状结构。 在两个鳍状结构之间的电介质层中至少有两个空隙。 此外，本发明还提供了一种用于形成所述多栅极场效应晶体管的多栅场效应晶体管工艺，包括以下步骤。 在基板上形成两个鳍状结构。 电介质层覆盖基板和两个鳍状结构，其中在两个鳍状结构之间的电介质层中形成至少两个空隙。

公开(公告)号：US20150064896A1

公开(公告)日：2015-03-05

申请号：US14013429

申请日：2013-08-29

Applicant: United Microelectronics Corp.

Inventor： Hung-Lin Shih ,  Chun-Yuan Wu ,  Chin-Fu Lin ,  Chih-Chien Liu

IPC: H01L21/28

CPC classification number: H01L21/02164 ,  H01L21/0217 ,  H01L21/30621 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628

Abstract: Provided is a method of fabricating a semiconductor device including the following steps. A dummy gate structure is formed on a substrate, wherein the dummy gate structure includes a dummy gate and a stacked hard mask, and the stacked hard mask includes from bottom to top a first hard mask layer and a second hard mask layer. A spacer is formed on a sidewall of the dummy gate structure. A mask layer is formed on the substrate. An opening corresponding to the second hard mask layer is formed in the mask layer. The second hard mask layer is removed. The mask layer is removed. A dry etch process is performed to remove the first hard mask layer, wherein the dry etch process uses NF3 and H2 as etchants.

Abstract translation: 提供一种制造半导体器件的方法，包括以下步骤。 在基板上形成虚拟栅极结构，其中虚拟栅极结构包括虚拟栅极和堆叠的硬掩模，并且堆叠的硬掩模从底部至顶部包括第一硬掩模层和第二硬掩模层。 在虚拟栅极结构的侧壁上形成间隔物。 在基板上形成掩模层。 在掩模层中形成与第二硬掩模层对应的开口。 去除第二个硬掩模层。 去除掩模层。 执行干蚀刻工艺以去除第一硬掩模层，其中干蚀刻工艺使用NF 3和H 2作为蚀刻剂。

公开(公告)号：US20140367779A1

公开(公告)日：2014-12-18

申请号：US13917623

申请日：2013-06-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chin-Fu Lin ,  Chih-Chien Liu ,  Chia-Lin Hsu

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/78696

Abstract: A semiconductor structure includes a fin-shaped structure and a gate. The fin-shaped structure is located in a substrate, wherein the fin-shaped structure has a through hole located right below a vacant part. The gate surrounds the vacant part. Moreover, the present invention also provides a semiconductor process including the following steps for forming said semiconductor structure. A substrate is provided. A fin-shaped structure is formed in the substrate, wherein the fin-shaped structure has a bottom part and a top part. A part of the bottom part is removed to form a vacant part in the corresponding top part, thereby forming the vacant part over a through hole. A gate is formed to surround the vacant part.

Abstract translation: 半导体结构包括鳍状结构和栅极。 鳍状结构位于基板中，其中鳍状结构具有位于空部分正下方的通孔。 门围绕着空的部分。 此外，本发明还提供一种半导体工艺，包括用于形成所述半导体结构的以下步骤。 提供基板。 在基板上形成翅片状结构，其中，翅片状结构具有底部和顶部。 底部的一部分被去除以在相应的顶部形成空的部分，从而在通孔上形成空的部分。 形成围绕空闲部分的门。

公开(公告)号：US08853740B2

公开(公告)日：2014-10-07

申请号：US13905148

申请日：2013-05-30

Applicant: United Microelectronics Corp.

Inventor： Chan-Lon Yang ,  Ted Ming-Lang Guo ,  Chin-I Liao ,  Chin-Cheng Chien ,  Shu-Yen Chan ,  Chun-Yuan Wu

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/324 ,  H01L21/8234 ,  H01L21/306

CPC classification number: H01L29/7848 ,  H01L21/30608 ,  H01L21/3247 ,  H01L21/823425 ,  H01L29/6656 ,  H01L29/66636

Abstract: A strained silicon channel semiconductor structure comprises a substrate having an upper surface, a gate structure formed on the upper surface, at least one recess formed in the substrate at lateral sides of the gate structure, wherein the recess has at least one sidewall which has an upper sidewall and a lower sidewall concaved in the direction to the gate structure, and the included angle between the upper sidewall and horizontal plane ranges between 54.5°-90°, and an epitaxial layer filled into the two recesses.

Abstract translation: 应变硅沟道半导体结构包括具有上表面的衬底，形成在上表面上的栅极结构，在栅极结构的侧面处形成在衬底中的至少一个凹部，其中凹部具有至少一个侧壁，其具有 上侧壁和下侧壁在与栅极结构的方向上凹陷，并且上侧壁和水平面之间的夹角在54.5°-90°之间，并且填充到两个凹部中的外延层。

公开(公告)号：US11133418B2

公开(公告)日：2021-09-28

申请号：US16413425

申请日：2019-05-15

Applicant: United Microelectronics Corp.

Inventor： Yen-Chen Chen ,  Xiao Wu ,  Hai Tao Liu ,  Ming Hua Du ,  Shouguo Zhang ,  Yao-Hung Liu ,  Chin-Fu Lin ,  Chun-Yuan Wu

IPC: H01L29/786 ,  H01L29/24 ,  H01L29/66 ,  H01L29/45 ,  H01L29/417

Abstract: A semiconductor device includes an oxide semiconductor layer, disposed over a substrate. A source electrode of a metal nitride is disposed on the oxide semiconductor layer. A drain electrode of the metal nitride is disposed on the oxide semiconductor layer. A metal-nitride oxidation layer is formed on a surface of the source electrode and the drain electrode. A ratio of a thickness of the metal-nitride oxidation layer to a thickness of the drain electrode or the source electrode is equal to or less than 0.2.

公开(公告)号：US10763260B2

公开(公告)日：2020-09-01

申请号：US16216954

申请日：2018-12-11

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chien-Ting Ho ,  Shih-Fang Tzou ,  Chun-Yuan Wu ,  Li-Wei Feng ,  Yu-Chieh Lin ,  Ying-Chiao Wang ,  Tsung-Ying Tsai

IPC: H01L27/105 ,  H01L21/768 ,  H01L21/02 ,  H01L29/66 ,  H01L21/311 ,  H01L27/108 ,  H01L29/78 ,  H01L21/3105

Abstract: A semiconductor device includes a memory region, a plurality of bit lines in the memory region, a first low-k dielectric layer on each sidewall of each bit line, a plurality of storage node regions between the bit lines, and a second low-k dielectric layer surrounding each storage node region.

公开(公告)号：US10381228B2

公开(公告)日：2019-08-13

申请号：US14631807

申请日：2015-02-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ying Lin ,  Ted Ming-Lang Guo ,  Chin-Cheng Chien ,  Chih-Chien Liu ,  Hsin-Kuo Hsu ,  Chin-Fu Lin ,  Chun-Yuan Wu

IPC: H01L21/306 ,  H01L21/3065 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

Abstract: An epitaxial process applying light illumination includes the following steps. A substrate is provided. A dry etching process and a wet etching process are performed to form a recess in the substrate, wherein an infrared light illuminates while the wet etching process is performed. An epitaxial structure is formed in the recess.

公开(公告)号：US20180331044A1

公开(公告)日：2018-11-15

申请号：US15624498

申请日：2017-06-15

Applicant: United Microelectronics Corp.

Inventor： Yi-Yu Wu ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Bin-Siang Tsai

IPC: H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L23/53257 ,  H01L21/02068 ,  H01L21/02164 ,  H01L21/02175 ,  H01L21/02244 ,  H01L21/02252 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/53266 ,  H01L23/53295

Abstract: A semiconductor device including a tungsten contact structure formed in a first dielectric layer on a substrate is provided. The tungsten contact structure contains a seam structure. A tungsten oxide layer is formed at least on a sidewall of the seam structure.