公开(公告)号：US20210408368A1

公开(公告)日：2021-12-30

申请号：US16916037

申请日：2020-06-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Shih-Wei Su ,  Bin-Siang Tsai ,  Ting-An Chien

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/10 ,  H01L43/12

Abstract: A magnetic tunnel junction (MTJ) device includes a bottom electrode, a reference layer, a tunnel barrier layer, a free layer and a top electrode. The bottom electrode and the top electrode are facing each other. The reference layer, the tunnel barrier layer and the free layer are stacked from the bottom electrode to the top electrode, wherein the free layer includes a first ferromagnetic layer, a spacer and a second ferromagnetic layer, wherein the spacer is sandwiched by the first ferromagnetic layer and the second ferromagnetic layer, wherein the spacer includes oxidized spacer sidewall parts, the first ferromagnetic layer includes first oxidized sidewall parts, and the second ferromagnetic layer includes second oxidized sidewall parts. The present invention also provides a method of manufacturing a magnetic tunnel junction (MTJ) device.

公开(公告)号：US20210343789A1

公开(公告)日：2021-11-04

申请号：US17375021

申请日：2021-07-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Bin-Siang Tsai ,  Ya-Jyuan Hung ,  Chin-Chia Yang ,  Ting-An Chien

IPC: H01L27/24 ,  H01L27/28 ,  H01L45/00 ,  H01L51/00 ,  H01L51/05 ,  H01L51/10

Abstract: A memory cell includes a first conductive line, a lower electrode, a carbon nano-tube (CNT) layer, a middle electrode, a resistive layer, a top electrode and a second conductive line. The first conductive line is disposed over a substrate. The lower electrode is disposed over the first conductive line. The carbon nano-tube (CNT) layer is disposed over the lower electrode. The middle electrode is disposed over the carbon nano-tube layer, thereby the lower electrode, the carbon nano-tube (CNT) layer and the middle electrode constituting a nanotube memory part. The resistive layer is disposed over the middle electrode. The top electrode is disposed over the resistive layer, thereby the middle electrode, the resistive layer and the top electrode constituting a resistive memory part. The second conductive line is disposed over the top electrode.

公开(公告)号：US20210074917A1

公开(公告)日：2021-03-11

申请号：US16589148

申请日：2019-10-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Wei Su ,  Da-Jun Lin ,  Bin-Siang Tsai ,  Ya-Jyuan Hung ,  Ting-An Chien

IPC: H01L45/00 ,  H01L27/24

Abstract: A method of forming a resistive random access memory cell includes the following steps. A first electrode layer, a blanket resistive switching material layer and a second electrode layer are formed on a layer sequentially. The second electrode layer is patterned to form a second electrode. The blanket resistive switching material layer is patterned to form a resistive switching material layer. An oxygen implanting process is performed to implant oxygen in two sidewall parts of the resistive switching material layer.

公开(公告)号：US20200266095A1

公开(公告)日：2020-08-20

申请号：US16866360

申请日：2020-05-04

Applicant: United Microelectronics Corp.

Inventor： Da-Jun Lin ,  Bin-Siang Tsai ,  Chich-Neng Chang

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522

Abstract: A structure of semiconductor device includes a substrate, having a dielectric layer on top. The structure further includes at least two metal elements being adjacent, disposed in the dielectric layer, wherein an air gap is existing between the two metal elements. A porous dielectric layer is disposed over the substrate, sealing the air gap. An inter-layer dielectric layer disposed on the porous dielectric layer.

公开(公告)号：US20200185325A1

公开(公告)日：2020-06-11

申请号：US16212401

申请日：2018-12-06

Applicant: United Microelectronics Corp.

Inventor： Da-Jun Lin ,  Bin-Siang Tsai ,  San-Fu Lin

IPC: H01L23/532 ,  H01L23/528 ,  H01L21/764 ,  H01L21/768

Abstract: A structure of semiconductor device includes a substrate, having a dielectric layer on top. At least two metal elements are formed in the dielectric layer, wherein an air gap is between adjacent two of the metal elements. A cap layer is disposed over the substrate, wherein a portion of the cap layer above the adjacent two of the metal elements has a hydrophilic surface. An inter-layer dielectric layer is disposed on the cap layer. The inter-layer dielectric layer seals the air gap between the two metal elements. The air gap remains and extends higher than a top surface of the metal elements.

公开(公告)号：US12293941B2

公开(公告)日：2025-05-06

申请号：US17835983

申请日：2022-06-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Fu-Yu Tsai ,  Bin-Siang Tsai ,  Chung-Yi Chiu

IPC: H10D64/00 ,  H01L21/304 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/768

Abstract: A gallium nitride (GaN) device with field plate structure, including a substrate, a gate on the substrate and a passivation layer covering on the gate, a source and a drain on the substrate and the passivation layer, a stop layer on the source, the drain and the passivation layer, and dual-damascene interconnects connecting respectively with the source and the drain, wherein the dual-damascene interconnect is provided with a via portion under the stop layer and a trench portion on the stop layer, and the via portion is connected with the source or the drain, and the trench portion of one of the dual-damascene interconnects extends horizontally toward the drain and overlaps the gate below in vertical direction, thereby functioning as a field plate structure for the GaN device.

公开(公告)号：US20250125252A1

公开(公告)日：2025-04-17

申请号：US18516868

申请日：2023-11-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chin-Chia Yang ,  Da-Jun Lin ,  Fu-Yu Tsai ,  Bin-Siang Tsai

IPC: H01L23/522 ,  H01L21/768

Abstract: A semiconductor device includes a device layer, an interlayer dielectric layer disposed above the device layer, a first interconnection structure, a second interconnection structure, and a first dielectric layer. The interlayer dielectric layer includes a first portion and a second portion disposed above a first device region and a second device region, respectively. A top surface of the first portion is lower than a top surface of the second portion in a vertical direction. The first interconnection structure includes first conductive lines partly located in the first portion. The second interconnection structure includes second conductive lines located in the second portion. The first dielectric layer is disposed on the first portion, a part of the first dielectric layer is sandwiched between two adjacent first conductive lines, and a bottom surface of the first dielectric layer is lower than the top surface of the second portion in the vertical direction.

公开(公告)号：US12205909B2

公开(公告)日：2025-01-21

申请号：US18138752

申请日：2023-04-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Bin-Siang Tsai ,  Fu-Yu Tsai

IPC: H01L23/00

Abstract: A method for fabricating a semiconductor device includes the steps of first forming an aluminum (Al) pad on a substrate, forming a passivation layer on the substrate and an opening exposing the Al pad, forming a cobalt (Co) layer in the opening and on the Al pad, bonding a wire onto the Co layer, and then performing a thermal treatment process to form a Co—Pd alloy on the Al pad.

公开(公告)号：US12108691B2

公开(公告)日：2024-10-01

申请号：US18324173

申请日：2023-05-26

Applicant: United Microelectronics Corp.

Inventor： Chich-Neng Chang ,  Da-Jun Lin ,  Shih-Wei Su ,  Fu-Yu Tsai ,  Bin-Siang Tsai

IPC: H10N70/20 ,  H10B63/00 ,  H10N70/00

CPC classification number: H10N70/24 ,  H10B63/30 ,  H10N70/063 ,  H10N70/826 ,  H10N70/841

Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes a device substrate, a resistance variable layer and a top electrode. The bottom electrode is disposed on the device substrate. The resistance variable layer is disposed on the bottom electrode. The top electrode is disposed on the resistance variable layer. The bottom electrode is formed with a tensile stress, while the top electrode is formed with a compressive stress.

公开(公告)号：US12016250B2

公开(公告)日：2024-06-18

申请号：US17725511

申请日：2022-04-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Min-Hua Tsai ,  Tai-Cheng Hou ,  Fu-Yu Tsai ,  Bin-Siang Tsai

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01

CPC classification number: H10N50/80 ,  H10B61/00 ,  H10N50/01

Abstract: An MRAM structure includes a dielectric layer. A first MRAM, a second MRAM and a third MRAM are disposed on the dielectric layer, wherein the second MRAM is disposed between the first MRAM and the third MRAM, and the second MRAM includes an MTJ. Two gaps are respectively disposed between the first MRAM and the second MRAM and between the second MRAM and the third MRAM. Two tensile stress pieces are respectively disposed in each of the two gaps. A first compressive stress layer surrounds and contacts the sidewall of the MTJ entirely. A second compressive stress layer covers the openings of each of the gaps and contacts the two tensile material pieces.