公开(公告)号：US20230091153A1

公开(公告)日：2023-03-23

申请号：US17994375

申请日：2022-11-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Wei Chang ,  Chia-Ming Kuo ,  Po-Jen Chuang ,  Fu-Jung Chuang ,  Shao-Wei Wang ,  Yu-Ren Wang ,  Chia-Yuan Chang

IPC: H01L29/49 ,  H01L29/78 ,  H01L29/08 ,  H01L29/24 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28

Abstract: A method of forming a semiconductor device. A substrate having a fin structure is provided. A dummy gate is formed on the fin structure. A polymer block is formed adjacent to a corner between the dummy gate and the fin structure. The polymer block is subjected to a nitrogen plasma treatment, thereby forming a nitridation layer in proximity to a sidewall of the dummy gate under the polymer block. After subjecting the polymer block to the nitrogen plasma treatment, a seal layer is formed on the sidewall of the dummy gate and on the polymer block. An epitaxial layer is then grown on a source/drain region of the fin structure. The dummy gate is then replaced with a metal gate.

公开(公告)号：US20230041596A1

公开(公告)日：2023-02-09

申请号：US17968778

申请日：2022-10-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fu-Jung Chuang ,  Tsuo-Wen Lu ,  Chia-Ming Kuo ,  Po-Jen Chuang ,  Chi-Mao Hsu

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/78

Abstract: A semiconductor device includes a gate structure on a substrate, a first spacer on sidewalls of gate structure, a second spacer on sidewalls of the first spacer, a polymer block adjacent to the first spacer and on a corner between the gate structure and the substrate, an interfacial layer under the polymer block, and a source/drain region adjacent to two sides of the first spacer. Preferably, the polymer block is surrounded by the first spacer, the interfacial layer, and the second spacer.

公开(公告)号：US11545557B2

公开(公告)日：2023-01-03

申请号：US17225066

申请日：2021-04-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Wei Chang ,  Chia-Ming Kuo ,  Po-Jen Chuang ,  Fu-Jung Chuang ,  Shao-Wei Wang ,  Yu-Ren Wang ,  Chia-Yuan Chang

IPC: H01L29/49 ,  H01L29/78 ,  H01L29/08 ,  H01L29/24 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28

Abstract: A semiconductor device includes substrate having a fin structure thereon, a gate structure overlying the fin structure, a polymer block at a corner between the gate structure and the fin structure, and a source/drain region on the fin structure. The polymer block includes a nitridation layer in proximity to a sidewall of the gate structure.

公开(公告)号：US20220302279A1

公开(公告)日：2022-09-22

申请号：US17225066

申请日：2021-04-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Wei Chang ,  Chia-Ming Kuo ,  Po-Jen Chuang ,  Fu-Jung Chuang ,  Shao-Wei Wang ,  Yu-Ren Wang ,  Chia-Yuan Chang

IPC: H01L29/49 ,  H01L29/78 ,  H01L29/08 ,  H01L29/24 ,  H01L21/28 ,  H01L21/02 ,  H01L29/66

Abstract: A semiconductor device includes substrate having a fin structure thereon, a gate structure overlying the fin structure, a polymer block at a corner between the gate structure and the fin structure, and a source/drain region on the fin structure. The polymer block includes a nitridation layer in proximity to a sidewall of the gate structure.

公开(公告)号：US10797157B1

公开(公告)日：2020-10-06

申请号：US16503609

申请日：2019-07-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fu-Jung Chuang ,  Tsuo-Wen Lu ,  Chia-Ming Kuo ,  Po-Jen Chuang ,  Chi-Mao Hsu

IPC: H01L29/78 ,  H01L21/283 ,  H01L21/311 ,  H01L29/66 ,  H01L21/02

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a polymer block on a corner between the gate structure and the substrate; performing an oxidation process to form a first seal layer on sidewalls of the gate structure; and forming a source/drain region adjacent to two sides of the gate structure.

公开(公告)号：US10741455B2

公开(公告)日：2020-08-11

申请号：US16782083

申请日：2020-02-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fu-Jung Chuang ,  Ching-Ling Lin ,  Po-Jen Chuang ,  Yu-Ren Wang ,  Wen-An Liang ,  Chia-Ming Kuo ,  Guan-Wei Huang ,  Yuan-Yu Chung ,  I-Ming Tseng

IPC: H01L21/00 ,  H01L21/8238 ,  H01L21/762 ,  H01L27/092

Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure in the fin-shaped structure to divide the fin-shaped structure into a first portion and a second portion, and a gate structure on the SDB structure. Preferably, the SDB structure includes silicon oxycarbonitride (SiOCN), a concentration portion of oxygen in SiOCN is between 30% to 60%, and the gate structure includes a metal gate.

公开(公告)号：US10607897B2

公开(公告)日：2020-03-31

申请号：US16589032

申请日：2019-09-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fu-Jung Chuang ,  Ching-Ling Lin ,  Po-Jen Chuang ,  Yu-Ren Wang ,  Wen-An Liang ,  Chia-Ming Kuo ,  Guan-Wei Huang ,  Yuan-Yu Chung ,  I-Ming Tseng

IPC: H01L21/00 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/762

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region; removing part of the first fin-shaped structure to form a first trench; forming a dielectric layer in the first trench, wherein the dielectric layer comprises silicon oxycarbonitride (SiOCN); and planarizing the dielectric layer to form a first single diffusion break (SDB) structure.

公开(公告)号：US10559655B1

公开(公告)日：2020-02-11

申请号：US16210738

申请日：2018-12-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsu Ting ,  Chia-Ming Kuo ,  Fu-Jung Chuang ,  Chun-Wei Yu ,  Po-Jen Chuang ,  Yu-Ren Wang

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/51 ,  H01L21/768 ,  H01L29/78 ,  H01L21/764

Abstract: A semiconductor device comprises at least one gate structure disposed on a substrate; a first dielectric layer disposed on the substrate and contacting an outer sidewall of the at least one gate structure; a second dielectric layer having a L shape disposed on the first dielectric layer and contacting the outer sidewall of the at least one gate structure; an etch stop layer contacting the second dielectric layer, the first dielectric layer and the substrate, wherein the second dielectric layer has an upper portion and a lower portion contacting the upper portion, the upper portion extends along the outer sidewall, the lower portion extends from the outer sidewall to the etch stop layer; and an air gap between the second dielectric layer and the etch stop layer; wherein the first dielectric layer and the lower portion of the second dielectric layer have a same width.