公开(公告)号：US20150011090A1

公开(公告)日：2015-01-08

申请号：US13934236

申请日：2013-07-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Jui Liang ,  Po-Chao Tsao ,  Jun-Jie Wang ,  Chih-Sen Huang

IPC: H01L21/311

CPC classification number: H01L21/31144 ,  H01L21/3086 ,  H01L29/66795

Abstract: A fin-shaped structure forming process includes the following step. A first mandrel and a second mandrel are formed on a substrate. A first spacer material is formed to entirely cover the first mandrel, the second mandrel and the substrate. The exposed first spacer material is etched to form a first spacer on the substrate beside the first mandrel. A second spacer material is formed to entirely cover the first mandrel, the second mandrel and the substrate. The second spacer material and the first spacer material are etched to form a second spacer on the substrate beside the second mandrel and a third spacer including the first spacer on the substrate beside the first mandrel. The layout of the second spacer and the third spacer is transferred to the substrate, so a second fin-shaped structure and a first fin-shaped structure having different widths are formed respectively.

Abstract translation: 鳍状结构形成工序包括以下工序。 第一心轴和第二心轴形成在基底上。 形成第一间隔材料以完全覆盖第一心轴，第二心轴和基底。 蚀刻暴露的第一间隔物材料以在第一心轴旁边的基底上形成第一间隔物。 形成第二间隔材料以完全覆盖第一心轴，第二心轴和基底。 蚀刻第二间隔物材料和第一间隔物材料，以在第二心轴旁边的基底上形成第二间隔物，以及在第一心轴旁边的包括在基底上的第一间隔物的第三间隔物。 第二间隔物和第三间隔物的布局被转移到基底，因此分别形成具有不同宽度的第二鳍状结构和第一鳍状结构。

公开(公告)号：US08928112B2

公开(公告)日：2015-01-06

申请号：US14337170

申请日：2014-07-21

Applicant: United Microelectronics Corp.

Inventor： En-Chiuan Liou ,  Po-Chao Tsao ,  Chia-Jui Liang ,  Jia-Rong Wu

IPC: H01L29/00 ,  H01L29/06

CPC classification number: H01L29/0653 ,  H01L21/76224 ,  H01L21/76235 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649

Abstract: A shallow trench isolation (STI) and method of forming the same is provided. The STI structure includes an upper insulating portion and a lower insulating portion, where the lower insulating portion includes a first insulator and an insulating layer surrounding the first insulator, the upper insulating portion includes a second insulator and a buffer layer surrounding the second insulator. A part of the buffer layer interfaces between the first insulator and the second insulator, and the outer sidewall of the buffer layer and the sidewall of the first insulator are leveled.

Abstract translation: 提供浅沟槽隔离（STI）及其形成方法。 STI结构包括上绝缘部分和下绝缘部分，其中下绝缘部分包括第一绝缘体和围绕第一绝缘体的绝缘层，上绝缘部分包括第二绝缘体和围绕第二绝缘体的缓冲层。 缓冲层的一部分在第一绝缘体和第二绝缘体之间接合，缓冲层的外侧壁和第一绝缘体的侧壁平整。

公开(公告)号：US20140367780A1

公开(公告)日：2014-12-18

申请号：US13920093

申请日：2013-06-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Fang Hong ,  Po-Chao Tsao

IPC: H01L29/78

CPC classification number: H01L23/562 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/0692 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785 ,  H01L29/7851 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor integrated device includes a substrate, a plurality of active fins, and a plurality of first protecting fins. The substrate includes an active region, and the active fins are positioned in the active region. The active region is surrounded by the first protecting fins. The active fins and the first protecting fins all extend along a first direction.

Abstract translation: 半导体集成器件包括衬底，多个有源鳍片和多个第一保护鳍片。 衬底包括有源区，活性鳍位于有源区中。 有源区被第一保护鳍包围。 活动鳍片和第一保护翼片沿着第一方向全部延伸。

公开(公告)号：US20140332920A1

公开(公告)日：2014-11-13

申请号：US14337170

申请日：2014-07-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Po-Chao Tsao ,  Chia-Jui Liang ,  Jia-Rong Wu

IPC: H01L29/06

CPC classification number: H01L29/0653 ,  H01L21/76224 ,  H01L21/76235 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649

Abstract: A shallow trench isolation (STI) and method of forming the same is provided. The STI structure includes an upper insulating portion and a lower insulating portion, where the lower insulating portion includes a first insulator and an insulating layer surrounding the first insulator, the upper insulating portion includes a second insulator and a buffer layer surrounding the second insulator. Apart of the buffer layer interfaces between the first insulator and the second insulator, and the outer sidewall of the buffer layer and the sidewall of the first insulator are leveled.

Abstract translation: 提供浅沟槽隔离（STI）及其形成方法。 STI结构包括上绝缘部分和下绝缘部分，其中下绝缘部分包括第一绝缘体和围绕第一绝缘体的绝缘层，上绝缘部分包括第二绝缘体和围绕第二绝缘体的缓冲层。 除了第一绝缘体和第二绝缘体之间的缓冲层界面之外，缓冲层的外侧壁和第一绝缘体的侧壁被平整。

公开(公告)号：US20140302677A1

公开(公告)日：2014-10-09

申请号：US13859720

申请日：2013-04-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Ling Lin ,  Po-Chao Tsao ,  Chia-Jui Liang ,  Chien-Ting Lin

IPC: H01L21/311 ,  H01L21/3105

CPC classification number: H01L21/3086 ,  H01L21/823468 ,  H01L21/823864 ,  H01L29/66795

Abstract: A method for manufacturing semiconductor structures includes providing a substrate having a plurality of mandrel patterns and a plurality of dummy patterns, simultaneously forming a plurality of first spacers on sidewalls of the mandrel patterns and a plurality of second spacers on sidewalls of the dummy patterns, and removing the second spacers and the mandrel patterns to form a plurality of spacer patterns on the substrate.

Abstract translation: 一种用于制造半导体结构的方法，包括提供具有多个心轴图案和多个虚拟图案的基板，同时在心轴图案的侧壁上形成多个第一间隔件，在虚设图案的侧壁上形成多个第二间隔件，以及 移除第二间隔件和心轴图案以在基底上形成多个间隔图案。

公开(公告)号：US20140295650A1

公开(公告)日：2014-10-02

申请号：US13851113

申请日：2013-03-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Jung Li ,  Chia-Jui Liang ,  Po-Chao Tsao ,  Ching-Ling Lin ,  En-Chiuan Liou

IPC: H01L21/308 ,  H01L21/311 ,  H01L21/02

CPC classification number: H01L21/308 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/76229

Abstract: A method of fabricating a patterned structure of a semiconductor device is provided. First, a substrate having a first region and a second region is provided. A target layer, a hard mask layer and a first patterned mask layer are then sequentially formed on the substrate. A first etching process is performed by using the first patterned mask layer as an etch mask so that a patterned hard mask layer is therefore formed. Spacers are respectively formed on each sidewall of the patterned hard mask layer. Then, a second patterned mask layer is formed on the substrate. A second etching process is performed to etch the patterned hard mask layer in the second region. After the exposure of the spacers, the patterned hard mask layer is used as an etch mask and an exposed target layer is removed until the exposure of the corresponding substrate.

Abstract translation: 提供一种制造半导体器件的图案化结构的方法。 首先，提供具有第一区域和第二区域的基板。 然后在基板上顺序地形成目标层，硬掩模层和第一图案化掩模层。 通过使用第一图案化掩模层作为蚀刻掩模来执行第一蚀刻工艺，从而形成图案化的硬掩模层。 间隔物分别形成在图案化的硬掩模层的每个侧壁上。 然后，在基板上形成第二图案化掩模层。 执行第二蚀刻工艺以蚀刻第二区域中的图案化硬掩模层。 在间隔物曝光之后，将图案化的硬掩模层用作蚀刻掩模，并且去除曝光的目标层，直到相应的基板的曝光。

公开(公告)号：US20140273386A1

公开(公告)日：2014-09-18

申请号：US13802812

申请日：2013-03-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Chao Tsao ,  Chien-Ting Lin

IPC: H01L29/66

CPC classification number: H01L29/665 ,  H01L21/28247 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76897 ,  H01L21/823418 ,  H01L29/41783 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/7848

Abstract: A method of forming a metal silicide layer includes the following steps. At first, at least a gate structure, at least a source/drain region and a first dielectric layer are formed on a substrate, and the gate structure is aligned with the first dielectric layer. Subsequently, a cap layer covering the gate structure is formed, and the cap layer does not overlap the first dielectric layer and the source/drain region. Afterwards, the first dielectric layer is removed to expose the source/drain region, and a metal silicide layer totally covering the source/drain region is formed.

Abstract translation: 形成金属硅化物层的方法包括以下步骤。 首先，在基板上形成至少栅极结构，至少源极/漏极区域和第一电介质层，并且栅极结构与第一电介质层对准。 随后，形成覆盖栅极结构的覆盖层，并且覆盖层不与第一介电层和源极/漏极区重叠。 然后，去除第一电介质层以暴露源极/漏极区域，并且形成完全覆盖源极/漏极区域的金属硅化物层。

公开(公告)号：US20140252423A1

公开(公告)日：2014-09-11

申请号：US13784839

申请日：2013-03-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Chao Tsao ,  Chien-Ting Lin ,  Chien-Ming Lai ,  Chi-Mao Hsu

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/32115 ,  H01L21/823842 ,  H01L27/0922 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78 ,  H01L29/7833

Abstract: A manufacturing method of semiconductor devices having metal gate includes following steps. A substrate having a first semiconductor device and a second semiconductor device formed thereon is provided. The first semiconductor device includes a first gate trench and the second semiconductor device includes a second gate trench. A first work function metal layer is formed in the first gate trench and the second gate trench. A portion of the first work function metal layer is removed from the second gate trench. A second work function metal layer is formed in the first gate trench and the second gate trench. The second work function metal layer and the first work function metal layer include the same metal material. A third work function metal layer and a gap-filling metal layer are sequentially formed in the first gate trench and the second gate trench.

Abstract translation: 具有金属栅极的半导体器件的制造方法包括以下步骤。 提供了具有形成在其上的第一半导体器件和第二半导体器件的衬底。 第一半导体器件包括第一栅极沟槽，第二半导体器件包括第二栅极沟槽。 第一功函数金属层形成在第一栅极沟槽和第二栅极沟槽中。 第一功函数金属层的一部分从第二栅极沟槽去除。 在第一栅极沟槽和第二栅极沟槽中形成第二功函数金属层。 第二功函数金属层和第一功函数金属层包括相同的金属材料。 在第一栅极沟槽和第二栅极沟槽中依次形成第三功函数金属层和间隙填充金属层。

公开(公告)号：US20140151763A1

公开(公告)日：2014-06-05

申请号：US13705175

申请日：2012-12-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Po-Chao Tsao ,  Chieh-Te Chen

IPC: H01L23/532 ,  H01L29/78 ,  H01L21/768

CPC classification number: H01L21/76897 ,  H01L21/283 ,  H01L21/32115 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L29/165 ,  H01L29/41725 ,  H01L29/41758 ,  H01L29/41783 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/78 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a semiconductor structure including a substrate, a transistor, a first ILD layer, a second ILD layer, a first contact plug, second contact plug and a third contact plug. The transistor is disposed on the substrate and includes a gate and a source/drain region. The first ILD layer is disposed on the transistor. The first contact plug is disposed in the first ILD layer and a top surface of the first contact plug is higher than a top surface of the gate. The second ILD layer is disposed on the first ILD layer. The second contact plug is disposed in the second ILD layer and electrically connected to the first contact plug. The third contact plug is disposed in the first ILD layer and the second ILD layer and electrically connected to the gate. The present invention further provides a method of making the same.

Abstract translation: 本发明提供了一种半导体结构，其包括衬底，晶体管，第一ILD层，第二ILD层，第一接触插塞，第二接触插塞和第三接触插塞。 晶体管设置在衬底上并且包括栅极和源极/漏极区域。 第一ILD层设置在晶体管上。 第一接触插塞设置在第一ILD层中，并且第一接触插塞的顶表面高于栅极的顶表面。 第二ILD层设置在第一ILD层上。 第二接触插塞设置在第二ILD层中并电连接到第一接触插塞。 第三接触插塞设置在第一ILD层和第二ILD层中并且电连接到栅极。 本发明还提供了制备该方法的方法。

公开(公告)号：US20170077094A1

公开(公告)日：2017-03-16

申请号：US15358143

申请日：2016-11-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Chao Tsao

IPC: H01L27/088 ,  H01L27/06 ,  H01L29/40 ,  H01L49/02 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L27/0611 ,  H01L27/0629 ,  H01L28/20 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/408 ,  H01L29/7816 ,  H01L29/7817 ,  H01L29/7835 ,  H01L29/7851

Abstract: A semiconductor integrated circuit includes a substrate, a multi-gate transistor device positioned on the substrate, and an LDMOS device positioned on the substrate. The substrate includes a plurality of first isolation structures and a plurality of second isolation structures. A depth of the first isolation structures is smaller than a depth of the second isolation structures. The multi-gate transistor device includes a plurality of first fin structures and a first gate electrode. The first fin structures are parallel with each other and spaced apart from each other by the first isolation structures. The first gate electrode is intersectionally arranged with the first fin structures, and covers a portion of each first fin structure. The LDMOS device includes a second gate electrode covering on the substrate. The LDMOS device is electrically isolated from the multi-gate transistor device by another second isolation structure.

Abstract translation: 半导体集成电路包括衬底，位于衬底上的多栅极晶体管器件和位于衬底上的LDMOS器件。 衬底包括多个第一隔离结构和多个第二隔离结构。 第一隔离结构的深度小于第二隔离结构的深度。 多栅晶体管器件包括多个第一鳍结构和第一栅电极。 第一鳍片结构彼此平行并且通过第一隔离结构彼此间隔开。 第一栅电极与第一鳍结构相交地布置，并且覆盖每个第一鳍结构的一部分。 LDMOS器件包括覆盖在衬底上的第二栅电极。 LDMOS器件通过另一第二隔离结构与多栅极晶体管器件电隔离。