公开(公告)号：US10453938B2

公开(公告)日：2019-10-22

申请号：US15846150

申请日：2017-12-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ling Wang ,  Ping-Hung Chiang ,  Chang-Po Hsiung ,  Chia-Wen Lu ,  Nien-Chung Li ,  Wen-Fang Lee ,  Chih-Chung Wang

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/08 ,  H01L29/78 ,  H01L21/311 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/06

Abstract: A transistor with dual spacers includes a gate, a first dual spacer and a second inner spacer. The gate is disposed on a substrate, wherein the gate includes a gate dielectric layer and a gate electrode, and the gate dielectric layer protrudes from the gate electrode and covers the substrate. The first dual spacer is disposed on the gate dielectric layer beside the gate, wherein the first dual spacer includes a first inner spacer and a first outer spacer. The second inner spacer having an L-shaped profile is disposed on the gate dielectric layer beside the first dual spacer. The present invention also provides a method of forming said transistor with dual spacers.

公开(公告)号：US20190103460A1

公开(公告)日：2019-04-04

申请号：US15720204

申请日：2017-09-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Po Hsiung ,  Ping-Hung Chiang ,  Chia-Lin Wang ,  Chia-Wen Lu ,  Nien-Chung Li ,  Wen-Fang Lee ,  Chih-Chung Wang

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/78

Abstract: A semiconductor transistor device is provided. The semiconductor transistor device includes a semiconductor substrate, a gate structure, a first isolation structure, a first doped region, and a first extra-contact structure. The gate structure is disposed on the semiconductor substrate, and the semiconductor substrate has a first region and a second region respectively located on two opposite sides of the gate structure. The first isolation structure and the first doped region are disposed in the first region of the semiconductor substrate. The first extra-contact structure is disposed on the semiconductor structure. The first extra-contact structure is located between the gate structure and the first doped region and penetrating into the first isolation structure in the first region of the semiconductor substrate, and the first doped region is electrically coupled to the first extra-contact structure.

公开(公告)号：US09972678B2

公开(公告)日：2018-05-15

申请号：US15287535

申请日：2016-10-06

Applicant: United Microelectronics Corp.

Inventor： Chang-Po Hsiung ,  Ping-Hung Chiang ,  Shih-Chieh Pu ,  Chia-Lin Wang ,  Nien-Chung Li ,  Wen-Fang Lee ,  Shih-Yin Hsiao ,  Chih-Chung Wang

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/51 ,  H01L21/762 ,  H01L21/311

CPC classification number: H01L29/0649 ,  H01L21/31111 ,  H01L21/7621 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/42364 ,  H01L29/513 ,  H01L29/517

Abstract: A method of forming a semiconductor device is provided including the following steps. A substrate having a first voltage area and a second voltage area is provided. A first oxide layer is formed in the first voltage area. The first oxide layer is removed to form a recess in the first voltage area. A shallow trench isolation (STI) structure is formed in the substrate, wherein a first portion of the STI structure is located in the first voltage area and a second portion of the STI structure is located in the second voltage area, a top surface of the STI structure is higher than the top surface of the substrate, and a bottom surface of the first portion of the STI structure in the first voltage area is lower than a bottom surface of the second portion of the STI structure in the second voltage area.

公开(公告)号：US09852952B2

公开(公告)日：2017-12-26

申请号：US14925955

申请日：2015-10-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Chung Wang ,  Shih-Yin Hsiao ,  Wen-Fang Lee ,  Nien-Chung Li ,  Shu-Wen Lin

IPC: H01L21/8234 ,  H01L21/28 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/3213 ,  H01L21/321 ,  H01L29/49 ,  H01L29/06 ,  H01L27/088

CPC classification number: H01L21/82345 ,  H01L21/28035 ,  H01L21/31051 ,  H01L21/32115 ,  H01L21/32139 ,  H01L21/823842 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/4916 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7834

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a logic region and high-voltage (HV) region; forming a first gate structure on the logic region and a second gate structure on the HV region; forming an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; forming a patterned hard mask on the HV region; and transforming the first gate structure into a metal gate.

公开(公告)号：US20170330948A1

公开(公告)日：2017-11-16

申请号：US15668708

申请日：2017-08-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Ching-Chung Yang ,  Wen-Fang Lee ,  Nien-Chung Li ,  Chih-Chung Wang

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/06 ,  H01L23/535 ,  G06F17/50

CPC classification number: H01L29/4238 ,  G06F17/5072 ,  H01L23/535 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/4983 ,  H01L29/66795 ,  H01L29/7816 ,  H01L29/7834 ,  H01L29/7835 ,  H01L29/7836 ,  H01L29/785

Abstract: A method of forming a gate layout includes providing a gate layout design diagram comprising at least one gate pattern, disposing at least one insulating plug pattern in the gate pattern for producing a modified gate layout in a case where any one of a length and a width of the gate pattern is greater than or equal to a predetermined size, and outputting and manufacturing the modified gate layout onto a photomask. The predetermined size is determined by a process ability limit, and the process ability limit is a smallest gate size causing gate dishing when a chemical mechanical polishing process is performed to a gate.

公开(公告)号：US09741850B1

公开(公告)日：2017-08-22

申请号：US15235320

申请日：2016-08-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Ching-Chung Yang ,  Ping-Hung Chiang ,  Nien-Chung Li ,  Wen-Fang Lee ,  Chih-Chung Wang ,  Kuan-Liang Liu ,  Kai-Kuen Chang

IPC: H01L29/745 ,  H01L29/76 ,  H01L23/58 ,  H01L21/00 ,  H01L21/336 ,  H01L29/78 ,  H01L29/06 ,  H01L21/768 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/7835 ,  H01L21/76895 ,  H01L21/823437 ,  H01L21/823462 ,  H01L29/1087 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/66492 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/7834

Abstract: A semiconductor device having a substrate, a gate electrode, a source and a drain, and a buried gate dielectric layer is disclosed. The buried gate dielectric layer is disposed below said gate electrode and protrudes therefrom to said drain, thereby separating said gate electrode and said drain by a substantial distance to reduce gate induced drain leakage.

公开(公告)号：US09196695B2

公开(公告)日：2015-11-24

申请号：US14273538

申请日：2014-05-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Huang Yu ,  Shih-Yin Hsiao ,  Wen-Fang Lee ,  Shu-Wen Lin ,  Kuan-Chuan Chen

IPC: H01L29/76 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  H01L29/08 ,  H01L21/266 ,  H01L21/28

CPC classification number: H01L29/42368 ,  H01L21/26506 ,  H01L21/266 ,  H01L21/28026 ,  H01L21/28158 ,  H01L21/2822 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/401 ,  H01L29/6659 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7834

Abstract: The present invention provides a high-voltage metal-oxide-semiconductor (HVMOS) transistor comprising a substrate, a gate dielectric layer, a gate electrode and a source and drain region. The gate dielectric layer is disposed on the substrate and includes a protruded portion and a recessed portion, wherein the protruded portion is disposed adjacent to two sides of the recessed portion and has a thickness greater than a thickness of the recessed portion. The gate electrode is disposed on the gate dielectric layer. Thus, the protruded portion of the gate dielectric layer can maintain a higher breakdown voltage, thereby keeping the current from leaking through the gate.

Abstract translation: 本发明提供一种高压金属氧化物半导体（HVMOS）晶体管，其包括衬底，栅极电介质层，栅极电极和源极和漏极区域。 栅介质层设置在基板上，并且包括突出部分和凹陷部分，其中突出部分邻近凹部的两侧设置，并且具有大于凹部的厚度的厚度。 栅电极设置在栅介质层上。 因此，栅极电介质层的突出部分可以保持更高的击穿电压，从而保持电流不通过栅极泄漏。

公开(公告)号：US20140159155A1

公开(公告)日：2014-06-12

申请号：US14181733

申请日：2014-02-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Tsung Lee ,  Cheng-Hua Yang ,  Wen-Fang Lee ,  Chih-Chung Wang ,  Chih-Wei Hsu ,  Po-Ching Chuang

IPC: H01L29/78

CPC classification number: H01L29/7816 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/404 ,  H01L29/42368

Abstract: A layout pattern of an implant layer includes at least a linear region and at least a non-linear region. The linear region includes a plurality of first patterns to accommodate first dopants and the non-linear region includes a plurality of second patterns to accommodate the first dopants. The linear region abuts the non-linear region. Furthermore, a pattern density of the first patterns in the linear region is smaller than a pattern density of the second patterns in the non-linear region.

Abstract translation: 植入层的布局图案至少包括线性区域和至少非线性区域。 线性区域包括容纳第一掺杂剂的多个第一图案，并且非线性区域包括多个第二图案以容纳第一掺杂剂。 线性区域邻接非线性区域。 此外，线性区域中的第一图案的图案密度小于非线性区域中的第二图案的图案密度。

公开(公告)号：US20250102922A1

公开(公告)日：2025-03-27

申请号：US18382528

申请日：2023-10-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Hung Li ,  Ruei-Jhe Tsao ,  Shan-Shi Huang ,  Wen-Fang Lee ,  Chiu-Te Lee

IPC: G03F7/00 ,  H01L21/027 ,  H01L21/033

Abstract: The invention provides an exposure method of semiconductor patterns, which comprises the following steps: providing a substrate, performing a first exposure step with a first photomask, forming a first pattern in a first region on the substrate, and performing a second exposure step with a second photomask, forming a second pattern in a second region on the substrate, the first pattern and the second pattern are in contact with each other, and at an interface of the first region And the second region, the first pattern and the second pattern are aligned with each other.

公开(公告)号：US20240234572A1

公开(公告)日：2024-07-11

申请号：US18108019

申请日：2023-02-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang-An Huang ,  Ming-Hua Tsai ,  Wen-Fang Lee ,  Chin-Chia Kuo ,  Jung Han ,  Chun-Lin Chen ,  Ching-Chung Yang ,  Nien-Chung Li

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L29/7835 ,  H01L29/1033 ,  H01L29/42364 ,  H01L29/7801

Abstract: An extended drain metal oxide semiconductor transistor includes a substrate. A gate is disposed on the substrate. A source doped region is disposed in the substrate at one side of the gate. A drain doped region is disposed in the substrate at another side of the gate. A thin gate dielectric layer is disposed under the gate. A thick gate dielectric layer is disposed under the gate. The thick gate dielectric layer extends from the bottom of the gate to contact the drain doped region. A second conductive type first well is disposed in the substrate and surrounds the source doped region and the drain doped region. A deep well is disposed within the substrate and surrounds the second conductive type first well.