公开(公告)号：US10923586B2

公开(公告)日：2021-02-16

申请号：US16521548

申请日：2019-07-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Huai-Tzu Chiang ,  Sheng-Hao Lin ,  Kuan-Hung Liu

IPC: H01L29/778 ,  H01L29/45 ,  H01L29/423 ,  H01L29/66 ,  H01L29/12 ,  H01L29/772

Abstract: A high electron mobility transistor (HEMT) includes a buffer layer, a carrier transit layer, a carrier supply layer, a gate, a source electrode and a drain electrode. The buffer layer is on a substrate. The carrier transit layer is on the buffer layer. The carrier supply layer is on the carrier transit layer. The gate is on the carrier supply layer. The source electrode and the drain electrode are at two opposite sides of the gate, wherein each of the source electrode and the drain electrode includes a conductive layer and a conductive oxide layer stacked from bottom to top.

公开(公告)号：US20210020767A1

公开(公告)日：2021-01-21

申请号：US16521548

申请日：2019-07-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Huai-Tzu Chiang ,  Sheng-Hao Lin ,  Kuan-Hung Liu

IPC: H01L29/778 ,  H01L29/45 ,  H01L29/423

Abstract: A high electron mobility transistor (HEMT) includes a buffer layer, a carrier transit layer, a carrier supply layer, a gate, a source electrode and a drain electrode. The buffer layer is on a substrate. The carrier transit layer is on the buffer layer. The carrier supply layer is on the carrier transit layer. The gate is on the carrier supply layer. The source electrode and the drain electrode are at two opposite sides of the gate, wherein each of the source electrode and the drain electrode includes a conductive layer and a conductive oxide layer stacked from bottom to top.

公开(公告)号：US10439023B2

公开(公告)日：2019-10-08

申请号：US16040319

申请日：2018-07-19

Applicant: United Microelectronics Corp.

Inventor： Huai-Tzu Chiang ,  Sheng-Hao Lin ,  Hao-Ming Lee ,  Yu-Ru Yang ,  Shih-Hsien Huang ,  Chien-Hung Chen ,  Chun-Yuan Wu ,  Cheng-Tzung Tsai

IPC: H01L29/76 ,  H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L21/225 ,  H01L21/768

Abstract: Provided is a FinFET including a substrate, at least one fin and at least one gate. A portion of the at least one fin is embedded in the substrate. The at least one fin includes, from bottom to top, a seed layer, a stress relaxation layer and a channel layer. The at least one gate is across the at least one fin. A method of forming a FinFET is further provided.

公开(公告)号：US09666687B1

公开(公告)日：2017-05-30

申请号：US15187795

申请日：2016-06-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hao-Ming Lee ,  Sheng-Hao Lin ,  Huai-Tzu Chiang

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/06 ,  H01L21/311

CPC classification number: H01L29/66666 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/31144 ,  H01L29/0649 ,  H01L29/0676 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7827

Abstract: The present invention provides a method for forming a semiconductor structure, at least including the following steps: first, four sacrificial patterns are formed on a substrate, and a plurality of spacers are then formed surrounding each sacrificial pattern. Next, the four sacrificial patterns are removed, and a photoresist layer is formed between each spacer, covering parts of each spacer. Afterwards, a first etching process is performed to partially remove each spacer, and the photoresist layer is then removed, and a second etching process is then performed, to remove each spacer again, and to form four nanowire hard masks.

公开(公告)号：US20170104070A1

公开(公告)日：2017-04-13

申请号：US14940867

申请日：2015-11-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Hung Chen ,  Shih-Hsien Huang ,  Yu-Ru Yang ,  Huai-Tzu Chiang ,  Hao-Ming Lee ,  Sheng-Hao Lin ,  Cheng-Tzung Tsai ,  Chun-Yuan Wu

IPC: H01L29/165 ,  H01L21/306 ,  H01L21/3065 ,  H01L29/06 ,  H01L21/02

CPC classification number: H01L29/165 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/30604 ,  H01L21/3065 ,  H01L29/0657 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device comprises a semiconductor substrate and a semiconductor fin. The semiconductor substrate has an upper surface and a recess extending downwards into the semiconductor substrate from the upper surface. The semiconductor fin is disposed in the recess and extends upwards beyond the upper surface, wherein the semiconductor fin is directly in contact with semiconductor substrate, so as to form at least one semiconductor hetero-interface on a sidewall of the recess.

公开(公告)号：US09281400B1

公开(公告)日：2016-03-08

申请号：US14726620

申请日：2015-06-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Huai-Tzu Chiang ,  Sheng-Hao Lin ,  Hsin-Yu Chen ,  Hao-Ming Lee ,  Tzyy-Ming Cheng

IPC: H01L21/339 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L29/7848 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823493 ,  H01L21/8258

Abstract: A method of fabricating a semiconductor device with fin-shaped structures includes respectively forming first fin-shaped structures in a first region and a second region of a semiconductor substrate, depositing a dielectric layer to completely cover the first fin-shaped structures, removing the first fin-shaped structures in the second region so as to form trenches in the dielectric layer, and performing an in-situ doping epitaxial growth process so as to respectively form second fin-shaped structures in the trenches.

Abstract translation: 制造具有鳍状结构的半导体器件的方法包括分别在半导体衬底的第一区域和第二区域中形成第一鳍状结构，沉积介电层以完全覆盖第一鳍状结构，去除第一 在第二区域中形成鳍状结构，以便在电介质层中形成沟槽，并且进行原位掺杂外延生长工艺以在沟槽中分别形成第二鳍状结构。