公开(公告)号：US20200266335A1

公开(公告)日：2020-08-20

申请号：US16297704

申请日：2019-03-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Ying-Cheng Liu ,  Yi-An Shih ,  Yi-Hui Lee ,  Chen-Yi Weng ,  Chin-Yang Hsieh ,  I-Ming Tseng ,  Jing-Yin Jhang ,  Yu-Ping Wang

IPC: H01L43/02 ,  H01L27/22

Abstract: A semiconductor device preferably includes a metal-oxide semiconductor (MOS) transistor disposed on a substrate, an interlayer dielectric (ILD) layer disposed on the MOS transistor, and a magnetic tunneling junction (MTJ) disposed on the ILD layer. Preferably, a top surface of the MTJ includes a reverse V-shape while the top surface of the MTJ is also electrically connected to a source/drain region of the MOS transistor.

公开(公告)号：US20200227625A1

公开(公告)日：2020-07-16

申请号：US16261524

申请日：2019-01-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Yi-Wei Tseng ,  Meng-Jun Wang ,  Chen-Yi Weng ,  Chin-Yang Hsieh ,  Jing-Yin Jhang ,  Yu-Ping Wang ,  Chien-Ting Lin ,  Ying-Cheng Liu ,  Yi-An Shih ,  Yi-Hui Lee ,  I-Ming Tseng

IPC: H01L43/02 ,  H01L27/22

Abstract: A magneto-resistive random access memory (MRAM) cell includes a substrate having a dielectric layer disposed thereon, a conductive via disposed in the dielectric layer, and a cylindrical stack disposed on the conductive via. The cylindrical stack includes a bottom electrode, a magnetic tunneling junction (MTJ) layer on the bottom electrode, and a top electrode on the MTJ layer. A spacer layer is disposed on a sidewall of the cylindrical stack. The top electrode protrudes from a top surface of the spacer layer.

公开(公告)号：US12284812B2

公开(公告)日：2025-04-22

申请号：US18636306

申请日：2024-04-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Yu-Ping Wang ,  Chen-Yi Weng ,  Chin-Yang Hsieh ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Yi-An Shih ,  I-Ming Tseng ,  Jing-Yin Jhang ,  Chien-Ting Lin

IPC: H10B61/00 ,  G11C11/16 ,  H10N50/01 ,  H10N50/80

Abstract: A semiconductor structure includes a substrate, a first dielectric layer on the substrate, a plurality of memory stack structures on the first dielectric layer, an insulating layer conformally covering the memory stack structures and the first dielectric layer, a second dielectric layer on the insulating layer and filling the spaces between the memory stack structures, a first interconnecting structure through the second dielectric layer, wherein a top surface of the first interconnecting structure is flush with a top surface of the second dielectric layer and higher than top surfaces of the memory stack structures, a third dielectric layer on the second dielectric layer, and a plurality of second interconnecting structures through the third dielectric layer, the second dielectric layer and the insulating layer on the top surfaces of the memory stack structures to contact the top surfaces of the memory stack structures.

公开(公告)号：US20250113494A1

公开(公告)日：2025-04-03

申请号：US18979625

申请日：2024-12-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Yi-An Shih ,  Bin-Siang Tsai ,  Fu-Yu Tsai

IPC: H10B61/00 ,  H10N50/01 ,  H10N50/80

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) on a substrate, forming a top electrode on the MTJ, forming an inter-metal dielectric (IMD) layer around the top electrode and the MTJ, forming a landing layer on the IMD layer and the MTJ, and then patterning the landing layer to form a landing pad. Preferably, the landing pad is disposed on the top electrode and the IMD layer adjacent to one side of the top electrode.

公开(公告)号：US12156408B2

公开(公告)日：2024-11-26

申请号：US18515289

申请日：2023-11-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Wei Wang ,  Yi-An Shih ,  Huan-Chi Ma

IPC: H10B61/00 ,  H10N50/85

Abstract: A semiconductor device includes a sense amplifier, a first magnetic tunneling junction (MTJ) connected to the sense amplifier at a first distance, a second MTJ connected to the sense amplifier at a second distance, and a third MTJ connected to the sense amplifier at a third distance. Preferably, the first distance is less than the second distance, the second distance is less than the third distance, a critical dimension of the first MTJ is less than a critical dimension of the second MTJ, and the critical dimension of the second MTJ is less than a critical dimension of the third MTJ.

公开(公告)号：US20240357943A1

公开(公告)日：2024-10-24

申请号：US18760005

申请日：2024-06-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chiu-Jung Chiu ,  Ya-Sheng Feng ,  I-Ming Tseng ,  Yi-An Shih ,  Yu-Chun Chen ,  Yi-Hui Lee ,  Chung-Liang Chu ,  Hsiu-Hao Hu

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01 ,  H10N50/85

CPC classification number: H10N50/80 ,  H10B61/00 ,  H10N50/01 ,  H10N50/85

Abstract: A method for fabricating semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a trench in the IMD layer, forming a synthetic antiferromagnetic (SAF) layer in the trench, forming a metal layer on the SAF layer, planarizing the metal layer and the SAF layer to form a metal interconnection, and forming a magnetic tunneling junction (MTJ) on the metal interconnection.

公开(公告)号：US20240032439A1

公开(公告)日：2024-01-25

申请号：US18373295

申请日：2023-09-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Chen-Yi Weng ,  Chin-Yang Hsieh ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Yi-An Shih ,  Jing-Yin Jhang ,  I-Ming Tseng ,  Yu-Ping Wang ,  Chien-Ting Lin ,  Kun-Chen Ho ,  Yi-Syun Chou ,  Chang-Min Li ,  Yi-Wei Tseng ,  Yu-Tsung Lai ,  JUN XIE

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01

CPC classification number: H10N50/80 ,  H10B61/00 ,  H10N50/01

Abstract: A method of fabricating magnetoresistive random access memory, including providing a substrate, forming a bottom electrode layer, a magnetic tunnel junction stack, a top electrode layer and a hard mask layer sequentially on the substrate, wherein a material of the top electrode layer is titanium nitride, a material of the hard mask layer is tantalum or tantalum nitride, and a percentage of nitrogen in the titanium nitride gradually decreases from a top surface of top electrode layer to a bottom surface of top electrode layer, and patterning the bottom electrode layer, the magnetic tunnel junction stack, the top electrode layer and the hard mask layer into multiple magnetoresistive random access memory cells.

公开(公告)号：US11812669B2

公开(公告)日：2023-11-07

申请号：US17835986

申请日：2022-06-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Chen-Yi Weng ,  Chin-Yang Hsieh ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Yi-An Shih ,  Jing-Yin Jhang ,  I-Ming Tseng ,  Yu-Ping Wang ,  Chien-Ting Lin ,  Kun-Chen Ho ,  Yi-Syun Chou ,  Chang-Min Li ,  Yi-Wei Tseng ,  Yu-Tsung Lai ,  Jun Xie

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01

CPC classification number: H10N50/80 ,  H10B61/00 ,  H10N50/01

Abstract: A magnetoresistive random access memory (MRAM), including a bottom electrode layer on a substrate, a magnetic tunnel junction stack on the bottom electrode layer, a top electrode layer on the magnetic tunnel junction stack, and a hard mask layer on said top electrode layer, wherein the material of top electrode layer is titanium nitride, a material of said hard mask layer is tantalum or tantalum nitride, and the percentage of nitrogen in the titanium nitride gradually decreases from the top surface of top electrode layer to the bottom surface of top electrode layer.

公开(公告)号：US20230329004A1

公开(公告)日：2023-10-12

申请号：US18209482

申请日：2023-06-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Yi-An Shih ,  Bin-Siang Tsai ,  Fu-Yu Tsai

IPC: H10B61/00 ,  H10N50/01 ,  H10N50/80

CPC classification number: H10B61/00 ,  H10N50/01 ,  H10N50/80

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) on a substrate, forming a top electrode on the MTJ, forming an inter-metal dielectric (IMD) layer around the top electrode and the MTJ, forming a landing layer on the IMD layer and the MTJ, and then patterning the landing layer to form a landing pad. Preferably, the landing pad is disposed on the top electrode and the IMD layer adjacent to one side of the top electrode.

公开(公告)号：US11508904B2

公开(公告)日：2022-11-22

申请号：US17308057

申请日：2021-05-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Chen-Yi Weng ,  Yi-Wei Tseng ,  Chin-Yang Hsieh ,  Jing-Yin Jhang ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Yi-An Shih ,  I-Ming Tseng ,  Yu-Ping Wang

IPC: H01L43/02 ,  H01L43/12 ,  H01L29/82 ,  G11C11/16 ,  H01L43/08 ,  G11C5/06 ,  H01L27/22

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first liner on the MTJ; forming a second liner on the first liner; forming an inter-metal dielectric (IMD) layer on the MTJ, and forming a metal interconnection in the IMD layer, the second liner, and the first liner to electrically connect the MTJ. Preferably, the first liner and the second liner are made of different materials.