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    Preservation circuit and methods to maintain values representing data in one or more layers of memory
    33.
    发明授权
    Preservation circuit and methods to maintain values representing data in one or more layers of memory 有权
    保存电路和保持在一层或多层存储器中表示数据的值的方法

    公开(公告)号：US09536607B2

    公开(公告)日：2017-01-03

    申请号：US14727190

    申请日：2015-06-01

    Applicant: Unity Semiconductor Corporation

    Inventor： Christophe Chevallier ,  Robert Norman

    IPC: G11C11/16 ,  G11C13/00 ,  G11C5/02 ,  G11C5/00

    CPC classification number: G11C13/0035 ,  G11C5/005 ,  G11C5/02 ,  G11C11/16 ,  G11C13/0002 ,  G11C13/0033 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2213/71 ,  G11C2213/77

    Abstract: Circuitry and methods for restoring data in memory are disclosed. The memory may include at least one layer of a non-volatile two-terminal cross-point array that includes a plurality of two-terminal memory elements that store data as a plurality of conductivity profiles and retain stored data in the absence of power. Over a period of time, logic values indicative of the stored data may drift such that if the logic values are not restored, the stored data may become corrupted. At least a portion of each memory may have data rewritten or restored by circuitry electrically coupled with the memory. Other circuitry may be used to determine a schedule for performing restore operations to the memory and the restore operations may be triggered by an internal or an external signal or event. The circuitry may be positioned in a logic layer and the memory may be fabricated over the logic layer.

    Abstract translation: 公开了用于恢复存储器中的数据的电路和方法。 存储器可以包括非易失性两端交叉点阵列的至少一层，其包括将数据存储为多个电导率分布并且在没有电力的情况下保存存储的数据的多个两端存储器元件。 在一段时间内，指示存储的数据的逻辑值可能漂移，使得如果逻辑值不被恢复，则所存储的数据可能被破坏。 每个存储器的至少一部分可以具有与存储器电耦合的电路重写或恢复的数据。 可以使用其他电路来确定用于对存储器执行恢复操作的调度，并且恢复操作可以由内部或外部信号或事件来触发。 电路可以定位在逻辑层中，并且存储器可以在逻辑层上制造。

    LOCAL BIT LINES AND METHODS OF SELECTING THE SAME TO ACCESS MEMORY ELEMENTS IN CROSS-POINT ARRAYS
    37.
    发明申请
    LOCAL BIT LINES AND METHODS OF SELECTING THE SAME TO ACCESS MEMORY ELEMENTS IN CROSS-POINT ARRAYS 有权
    本地位线及其选择方法可以在交叉点阵列中访问记忆元素

    公开(公告)号：US20150132917A1

    公开(公告)日：2015-05-14

    申请号：US14526894

    申请日：2014-10-29

    Applicant: UNITY SEMICONDUCTOR CORPORATION

    Inventor： Chang Hua Siau ,  Christophe Chevallier ,  Darrell Rinerson ,  Seow Fong Lim ,  Sri Rama Namala

    IPC: H01L45/00 ,  G11C13/00 ,  H01L27/24

    CPC classification number: G11C5/025 ,  G11C5/02 ,  G11C8/00 ,  G11C11/00 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2213/77 ,  H01L21/82 ,  H01L27/2481 ,  H01L45/16

    Abstract: Embodiments relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement a memory architecture that includes local bit lines for accessing subsets of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point memory array formed above a logic layer. The cross-point memory array includes X-lines and Y-lines, of which at least one Y-line includes groups of Y-line portions. Each of the Y-line portions can be arranged in parallel with other Y-line portions within a group of the Y-line portions. Also included are memory elements disposed between a subset of the X-lines and the group of the Y-line portions. In some embodiments, a decoder is configured to select a Y-line portion from the group of Y-line portions to access a subset of the memory elements.

    Abstract translation: 实施例通常涉及半导体和存储器技术，更具体地，涉及用于实现存储器架构的系统，集成电路和方法，该存储器架构包括用于访问诸如基于第三维存储器技术的存储器元件的存储器元件的子集的本地位线。 在至少一些实施例中，集成电路包括形成在逻辑层上方的交叉点存储器阵列。 交叉点存储器阵列包括X线和Y线，其中至少一条Y线包括Y线部分的组。 每个Y线部分可以与一组Y线部分内的其它Y线部分平行地布置。 还包括设置在X线的子集和Y线部分的组之间的存储器元件。 在一些实施例中，解码器被配置为从Y组部分组中选择Y线部分以访问存储器元件的子集。

    CIRCUITS AND TECHNIQUES TO COMPENSATE MEMORY ACCESS SIGNALS FOR VARIATIONS OF PARAMETERS IN MULTIPLE LAYERS OF MEMORY
    38.
    发明申请
    CIRCUITS AND TECHNIQUES TO COMPENSATE MEMORY ACCESS SIGNALS FOR VARIATIONS OF PARAMETERS IN MULTIPLE LAYERS OF MEMORY 有权
    补偿记忆多层参数变化的记忆访问信号的电路和技术

    公开(公告)号：US20150055425A1

    公开(公告)日：2015-02-26

    申请号：US14476632

    申请日：2014-09-03

    Applicant: UNITY SEMICONDUCTOR CORPORATION

    Inventor： Christophe Chevallier ,  Seow Fong Lim ,  Chang Hua Siau

    IPC: G11C7/22

    CPC classification number: G11C7/22 ,  B82Y30/00 ,  G11C5/02 ,  G11C7/04 ,  G11C8/10 ,  G11C8/12 ,  G11C11/21 ,  G11C13/0021

    Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.

    Abstract translation: 本发明的实施例一般涉及半导体和存储器技术，更具体地，涉及用于实现电路的系统，集成电路和方法，所述电路被配置为通过在存储器操作期间调整存取信号来补偿存储器层中的参数变化。 在一些实施例中，存储器单元基于第三维存储器技术。 在至少一些实施例中，集成电路包括多层存储器，包括半导体材料子层的层。 集成电路还包括被配置为生成访问信号以便于访问操作的访问信号发生器，以及被配置为调整多层存储器中的每层的访问信号的特征调整器。

    PRESERVATION CIRCUIT AND METHODS TO MAINTAIN VALUES REPRESENTING DATA IN ONE OR MORE LAYERS OF MEMORY
    39.
    发明申请
    PRESERVATION CIRCUIT AND METHODS TO MAINTAIN VALUES REPRESENTING DATA IN ONE OR MORE LAYERS OF MEMORY 有权
    保存电路和维护数值在一个或多个存储器中表示数据的方法

    公开(公告)号：US20140140123A1

    公开(公告)日：2014-05-22

    申请号：US14068754

    申请日：2013-10-31

    Applicant: Unity Semiconductor Corporation

    Inventor： Christophe Chevallier ,  Robert Norman

    IPC: G11C5/00

    CPC classification number: G11C13/0035 ,  G11C5/005 ,  G11C5/02 ,  G11C11/16 ,  G11C13/0002 ,  G11C13/0033 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2213/71 ,  G11C2213/77

    Abstract: Circuitry and methods for restoring data in memory are disclosed. The memory may include at least one layer of a non-volatile two-terminal cross-point array that includes a plurality of two-terminal memory elements that store data as a plurality of conductivity profiles and retain stored data in the absence of power. Over a period of time, logic values indicative of the stored data may drift such that if the logic values are not restored, the stored data may become corrupted. At least a portion of each memory may have data rewritten or restored by circuitry electrically coupled with the memory. Other circuitry may be used to determine a schedule for performing restore operations to the memory and the restore operations may be triggered by an internal or an external signal or event. The circuitry may be positioned in a logic layer and the memory may be fabricated over the logic layer.

    Abstract translation: 公开了用于恢复存储器中的数据的电路和方法。 存储器可以包括非易失性两端交叉点阵列的至少一层，其包括将数据存储为多个电导率分布并且在没有电力的情况下保存存储的数据的多个两端存储器元件。 在一段时间内，指示存储的数据的逻辑值可能漂移，使得如果逻辑值不被恢复，则所存储的数据可能被破坏。 每个存储器的至少一部分可以具有与存储器电耦合的电路重写或恢复的数据。 可以使用其他电路来确定用于对存储器执行恢复操作的调度，并且恢复操作可以由内部或外部信号或事件来触发。 电路可以定位在逻辑层中，并且存储器可以在逻辑层上制造。

    Circuits and techniques to compensate data signals for variations of parameters affecting memory cells in cross point arrays
    40.
    发明授权
    Circuits and techniques to compensate data signals for variations of parameters affecting memory cells in cross point arrays 有权
    用于补偿数据信号以影响交叉点阵列中影响存储器单元的参数变化的电路和技术

    公开(公告)号：US08705260B2

    公开(公告)日：2014-04-22

    申请号：US13728676

    申请日：2012-12-27

    Applicant: Unity Semiconductor Corporation

    Inventor： Christophe Chevallier ,  Seow Fong Lim ,  Chang Hua Siau

    IPC: G11C5/02 ,  G11C11/21

    CPC classification number: G11C7/22 ,  B82Y30/00 ,  G11C5/02 ,  G11C7/04 ,  G11C8/10 ,  G11C8/12 ,  G11C11/21 ,  G11C13/0021

    Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations that affect the operation of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point array comprising memory elements disposed among word lines and bit lines, where a parameter can affect the operating characteristics of a memory element. The integrated circuit further includes a data signal adjuster configured to modify the operating characteristic to compensate for a deviation from a target value for the operating characteristic based on the parameter. In some embodiments, the memory element, such as a resistive memory element, is configured to generate a data signal having a magnitude substantially at the target value independent of variation in the parameter.

    Abstract translation: 本发明的实施例一般涉及半导体和存储器技术，更具体地，涉及用于实现电路的系统，集成电路和方法，所述电路被配置为补偿影响存储器元件的操作的参数变化，诸如基于第三维存储器的存储器元件 技术。 在至少一些实施例中，集成电路包括交叉点阵列，其包括布置在字线和位线之间的存储器元件，其中参数可影响存储器元件的操作特性。 集成电路还包括数据信号调整器，其被配置为基于该参数来修改操作特性以补偿与操作特性的目标值的偏差。 在一些实施例中，诸如电阻性存储器元件的存储器元件被配置为产生具有与参数变化无关的基本上处于目标值的幅度的数据信号。

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