公开(公告)号：US20180342268A1

公开(公告)日：2018-11-29

申请号：US15984107

申请日：2018-05-18

Applicant: Unity Semiconductor Corporation

Inventor： Chang Hua Siau ,  Christophe Chevallier ,  Darrell Rinerson ,  Seow Fong Lim ,  Sri Rama Namala

IPC: G11C5/02 ,  H01L45/00 ,  G11C13/00 ,  G11C8/00 ,  H01L21/82 ,  G11C11/00 ,  H01L27/24

Abstract: Embodiments relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement a memory architecture that includes local bit lines for accessing subsets of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point memory array formed above a logic layer. The cross-point memory array includes X-lines and Y-lines, of which at least one Y-line includes groups of Y-line portions. Each of the Y-line portions can be arranged in parallel with other Y-line portions within a group of the Y-line portions. Also included are memory elements disposed between a subset of the X-lines and the group of the Y-line portions. In some embodiments, a decoder is configured to select a Y-line portion from the group of Y-line portions to access a subset of the memory elements.

公开(公告)号：US09806130B2

公开(公告)日：2017-10-31

申请号：US15393545

申请日：2016-12-29

Applicant: UNITY SEMICONDUCTOR CORPORATION

Inventor： Christophe J. Chevallier ,  Steve Kuo-Ren Hsia ,  Wayne Kinney ,  Steven Longcor ,  Darrell Rinerson ,  John Sanchez ,  Philip F. S. Swab ,  Edmond R. Ward

IPC: H01L45/00 ,  G11C11/56 ,  H01L27/24 ,  G11C13/00

CPC classification number: H01L27/2463 ,  G11C11/16 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/009 ,  G11C2213/15 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/77 ,  G11C2213/79 ,  H01L27/24 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1633 ,  H01L45/1658

Abstract: A re-writeable non-volatile memory device including a re-writeable non-volatile two-terminal memory element (ME) having tantalum. The ME including a first terminal, a second terminal, a first layer of a conductive metal oxide (CMO), and a second layer in direct contact with the first layer. The second layer and the first layer being operative to store at least one-bit of data as a plurality of resistive states, and the first and second layer are electrically in series with each other and with the first and second terminals.

公开(公告)号：US09837149B2

公开(公告)日：2017-12-05

申请号：US15181009

申请日：2016-06-13

Applicant: UNITY SEMICONDUCTOR CORPORATION

Inventor： Bruce Lynn Bateman ,  Christophe Chevallier ,  Darrell Rinerson ,  Chang Hua Siau

IPC: G11C17/00 ,  G11C13/00 ,  G11C7/12 ,  G11C7/22

CPC classification number: G11C13/004 ,  G11C7/12 ,  G11C7/22 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0009 ,  G11C13/0011 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0045 ,  G11C2013/0054 ,  G11C2213/11 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/53 ,  G11C2213/71 ,  G11C2213/77

Abstract: A low read current architecture for memory. Bit lines of a cross point memory array are allowed to be charged by a selected word line until a minimum voltage differential between a memory state and a reference level is assured.

公开(公告)号：US09831425B2

公开(公告)日：2017-11-28

申请号：US14844805

申请日：2015-09-03

Applicant: UNITY SEMICONDUCTOR CORPORATION

Inventor： Darrell Rinerson ,  Christophe J. Chevallier ,  Wayne Kinney ,  Roy Lambertson ,  John E. Sanchez, Jr. ,  Lawrence Schloss ,  Philip Swab ,  Edmond Ward

IPC: H01L45/00 ,  G06F17/50 ,  G11C11/56 ,  G11C13/00 ,  H01L27/24

CPC classification number: H01L45/08 ,  G06F17/5045 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0009 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0045 ,  G11C2013/005 ,  G11C2013/009 ,  G11C2213/11 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/53 ,  G11C2213/54 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1625

Abstract: A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric field effective to cause oxygen ionic motion.

公开(公告)号：US09159408B2

公开(公告)日：2015-10-13

申请号：US14167694

申请日：2014-01-29

Applicant: Unity Semiconductor Corporation

Inventor： Christophe J. Chevallier ,  Steve Kuo-Ren Hsia ,  Wayne Kinney ,  Steven Longcor ,  Darrell Rinerson ,  John Sanchez ,  Philip F. S. Swab ,  Edmond R. Ward

IPC: H01L45/00 ,  G11C13/00 ,  G11C11/16 ,  G11C11/56 ,  H01L27/24

CPC classification number: H01L27/2463 ,  G11C11/16 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/009 ,  G11C2213/15 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/77 ,  G11C2213/79 ,  H01L27/24 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1633 ,  H01L45/1658

Abstract: A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one or more layers of material. At least one of those layers of material can be a conductive oxide (e.g., a perovskite such as LaSrCoO3-LSCoO or LaNiO3-LNO) that is in contact with the CMO. The conductive oxide layer can be selected as a seed layer operative to provide a good lattice match with and/or a lower crystallization temperature for the CMO. The conductive oxide layer may also be in contact with a metal layer (e.g., Pt). The memory cell additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays, such as non-volatile two-terminal cross-point memory arrays.

Abstract translation: 公开了一种包括导电氧化物电极的存储单元。 存储单元包括用于将数据存储为多个电阻状态的存储元件。 存储元件包括与可包括一层或多层材料的电极接触的导电金属氧化物（CMO）（例如，钙钛矿）层。 这些材料层中的至少一层可以是与CMO接触的导电氧化物（例如，诸如LaSrCoO3-LSCoO或LaNiO3-LNO的钙钛矿）。 可以选择导电氧化物层作为晶种层，以为CMO提供良好的晶格匹配和/或较低的结晶温度。 导电氧化物层也可以与金属层（例如Pt）接触。 存储单元还具有非线性IV特性，这在某些阵列中是有利的，例如非易失性两端交叉点存储阵列。

公开(公告)号：US20150132917A1

公开(公告)日：2015-05-14

申请号：US14526894

申请日：2014-10-29

Applicant: UNITY SEMICONDUCTOR CORPORATION

Inventor： Chang Hua Siau ,  Christophe Chevallier ,  Darrell Rinerson ,  Seow Fong Lim ,  Sri Rama Namala

IPC: H01L45/00 ,  G11C13/00 ,  H01L27/24

CPC classification number: G11C5/025 ,  G11C5/02 ,  G11C8/00 ,  G11C11/00 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2213/77 ,  H01L21/82 ,  H01L27/2481 ,  H01L45/16

Abstract: Embodiments relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement a memory architecture that includes local bit lines for accessing subsets of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point memory array formed above a logic layer. The cross-point memory array includes X-lines and Y-lines, of which at least one Y-line includes groups of Y-line portions. Each of the Y-line portions can be arranged in parallel with other Y-line portions within a group of the Y-line portions. Also included are memory elements disposed between a subset of the X-lines and the group of the Y-line portions. In some embodiments, a decoder is configured to select a Y-line portion from the group of Y-line portions to access a subset of the memory elements.

Abstract translation: 实施例通常涉及半导体和存储器技术，更具体地，涉及用于实现存储器架构的系统，集成电路和方法，该存储器架构包括用于访问诸如基于第三维存储器技术的存储器元件的存储器元件的子集的本地位线。 在至少一些实施例中，集成电路包括形成在逻辑层上方的交叉点存储器阵列。 交叉点存储器阵列包括X线和Y线，其中至少一条Y线包括Y线部分的组。 每个Y线部分可以与一组Y线部分内的其它Y线部分平行地布置。 还包括设置在X线的子集和Y线部分的组之间的存储器元件。 在一些实施例中，解码器被配置为从Y组部分组中选择Y线部分以访问存储器元件的子集。

公开(公告)号：US09570515B2

公开(公告)日：2017-02-14

申请号：US14850702

申请日：2015-09-10

Applicant: Unity Semiconductor Corporation

Inventor： Christophe J. Chevallier ,  Steve Kuo-Ren Hsia ,  Wayne Kinney ,  Steven Longcor ,  Darrell Rinerson ,  John Sanchez ,  Philip F. S. Swab ,  Edmond R. Ward

IPC: H01L27/24 ,  H01L45/00 ,  G11C11/16 ,  G11C11/56 ,  G11C13/00

CPC classification number: H01L27/2463 ,  G11C11/16 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/009 ,  G11C2213/15 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/77 ,  G11C2213/79 ,  H01L27/24 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1633 ,  H01L45/1658

Abstract: A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one or more layers of material. At least one of those layers of material can be a conductive oxide (e.g., a perovskite such as LaSrCoO3-LSCoO or LaNiO3-LNO) that is in contact with the CMO. The conductive oxide layer can be selected as a seed layer operative to provide a good lattice match with and/or a lower crystallization temperature for the CMO. The conductive oxide layer may also be in contact with a metal layer (e.g., Pt). The memory cell additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays, such as non-volatile two-terminal cross-point memory arrays.

Abstract translation: 公开了一种包括导电氧化物电极的存储单元。 存储单元包括用于将数据存储为多个电阻状态的存储元件。 存储元件包括与可包括一层或多层材料的电极接触的导电金属氧化物（CMO）（例如，钙钛矿）层。 这些材料层中的至少一层可以是与CMO接触的导电氧化物（例如，诸如LaSrCoO3-LSCoO或LaNiO3-LNO的钙钛矿）。 可以选择导电氧化物层作为晶种层，以为CMO提供良好的晶格匹配和/或较低的结晶温度。 导电氧化物层也可以与金属层（例如Pt）接触。 存储单元还具有非线性IV特性，这在某些阵列中是有利的，例如非易失性两端交叉点存储阵列。

公开(公告)号：US20150380642A1

公开(公告)日：2015-12-31

申请号：US14844805

申请日：2015-09-03

Applicant: UNITY SEMICONDUCTOR CORPORATION

Inventor： Darrell Rinerson ,  Christophe J. Chevallier ,  Wayne Kinney ,  Roy Lambertson ,  John E. Sanchez, JR. ,  Lawrence Schloss ,  Philip Swab ,  Edmond Ward

IPC: H01L45/00

CPC classification number: H01L45/08 ,  G06F17/5045 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0009 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0045 ,  G11C2013/005 ,  G11C2013/009 ,  G11C2213/11 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/53 ,  G11C2213/54 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1625

Abstract: A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric field effective to cause oxygen ionic motion.

公开(公告)号：US20160372189A1

公开(公告)日：2016-12-22

申请号：US15181009

申请日：2016-06-13

Applicant: UNITY SEMICONDUCTOR CORPORATION

Inventor： Bruce Lynn Bateman ,  Christophe Chevallier ,  Darrell Rinerson ,  Chang Hua Siau

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C7/12 ,  G11C7/22 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0009 ,  G11C13/0011 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0045 ,  G11C2013/0054 ,  G11C2213/11 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/53 ,  G11C2213/71 ,  G11C2213/77

Abstract: A low read current architecture for memory. Bit lines of a cross point memory array are allowed to be charged by a selected word line until a minimum voltage differential between a memory state and a reference level is assured.

Abstract translation: 用于存储器的低读取当前体系结构。 允许交叉点存储器阵列的位线被选择的字线充电，直到确保存储器状态和参考电平之间的最小电压差。

公开(公告)号：US20140211542A1

公开(公告)日：2014-07-31

申请号：US14167694

申请日：2014-01-29

Applicant: Unity Semiconductor Corporation

Inventor： Christophe J. Chevallier ,  Steve Kuo-Ren Hsia ,  Wayne Kinney ,  Steven Longcor ,  Darrell Rinerson ,  John Sanchez ,  Philip F.S. Swab ,  Edmond R. Ward

IPC: G11C13/00

CPC classification number: H01L27/2463 ,  G11C11/16 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/009 ,  G11C2213/15 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/77 ,  G11C2213/79 ,  H01L27/24 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1633 ,  H01L45/1658

Abstract: A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one or more layers of material. At least one of those layers of material can be a conductive oxide (e.g., a perovskite such as LaSrCoO3-LSCoO or LaNiO3-LNO) that is in contact with the CMO. The conductive oxide layer can be selected as a seed layer operative to provide a good lattice match with and/or a lower crystallization temperature for the CMO. The conductive oxide layer may also be in contact with a metal layer (e.g., Pt). The memory cell additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays, such as non-volatile two-terminal cross-point memory arrays.

Abstract translation: 公开了一种包括导电氧化物电极的存储单元。 存储单元包括用于将数据存储为多个电阻状态的存储元件。 存储元件包括与可包括一层或多层材料的电极接触的导电金属氧化物（CMO）（例如，钙钛矿）层。 这些材料层中的至少一层可以是与CMO接触的导电氧化物（例如，诸如LaSrCoO3-LSCoO或LaNiO3-LNO的钙钛矿）。 可以选择导电氧化物层作为晶种层，以为CMO提供良好的晶格匹配和/或较低的结晶温度。 导电氧化物层也可以与金属层（例如Pt）接触。 存储单元还具有非线性IV特性，这在某些阵列中是有利的，例如非易失性两端交叉点存储阵列。