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    Integrated circuit sensor
    33.
    发明授权
    Integrated circuit sensor 失效
    集成电路传感器

    公开(公告)号：US4674319A

    公开(公告)日：1987-06-23

    申请号：US714076

    申请日：1985-03-20

    Applicant: Richard S. Muller ,  Roger T. Howe

    Inventor： Richard S. Muller ,  Roger T. Howe

    IPC: G01N27/00 ,  H01L29/84

    CPC classification number: G01N29/036 ,  G01N2291/0256

    Abstract: A polysilicon microstructure is formed on a silicon substrate. Beneath the microstructure, are diffused regions in the substrate. The microstructure is capacitively coupled to these diffused regions so that one such capacitor acts as an excitation capacitor and the other capacitor acts as a sense capacitor. By applying an AC voltage to the excitation capacitor, the electrostatic force between the substrate and the microstructure changes causing a mechanical vibration in the microstructure. A DC voltage is applied to the sense capacitor. The mechanical vibration, which changes its capacitance, will develop a current through the sense capacitor. A phenomenon may then be sensed by the vibrating microstructure. A polymer film disposed on the microstructure can sorb a gas of interest. As the mass of the polymer film and vibrating microstructure increases, its frequency or phase changes. The current through the sense capacitor will exhibit a commensurate frequency or phase shift. Detection of such frequency or phase shift in the sense capacitor current will transduce the detection of the vapor of interest.

    Abstract translation: 在硅衬底上形成多晶硅微结构。 在微观结构之下，是底物中的扩散区域。 微结构电容耦合到这些扩散区域，使得一个这样的电容器用作激励电容器，另一个电容器用作感测电容器。 通过向激励电容器施加AC电压，衬底和微结构之间的静电力导致微结构中的机械振动。 直流电压被施加到感测电容器。 改变其电容的机械振动将产生通过感测电容器的电流。 然后可以通过振动微结构感测现象。 设置在微结构上的聚合物膜可吸附感兴趣的气体。 随着聚合物膜的质量和振动微结构的增加，其频率或相位发生变化。 通过感测电容器的电流将呈现相当的频率或相移。 感测电容器电流中的这种频率或相移的检测将转换感兴趣的蒸气的检测。

    Strained semiconductor materials, devices and methods therefore
    34.
    发明授权
    Strained semiconductor materials, devices and methods therefore 失效
    因此，应变半导体材料，器件和方法

    公开(公告)号：US08633573B2

    公开(公告)日：2014-01-21

    申请号：US12706112

    申请日：2010-02-16

    Applicant: Jinendra Raja Jain ,  Roger T. Howe

    Inventor： Jinendra Raja Jain ,  Roger T. Howe

    IPC: H01L29/06

    CPC classification number: H01L31/105 ,  H01L33/34

    Abstract: Various applications are directed to a material stack having a strained active material therein. In connection with an embodiment, an active material (e.g. a semiconductor material) is at least initially and partially released from and suspended over a substrate, strained, and held in place. The release and suspension facilitates the application of strain to the semiconductor material.

    Abstract translation: 各种应用涉及其中具有应变活性材料的材料堆叠。 结合一个实施例，活性材料（例如半导体材料）至少首先和部分地从衬底上释放并悬浮在衬底上，应变并保持就位。 释放和悬浮有助于将应变应用于半导体材料。

    PLANAR MICROSHELLS FOR VACUUM ENCAPSULATED DEVICES AND DAMASCENE METHOD OF MANUFACTURE
    36.
    发明申请
    PLANAR MICROSHELLS FOR VACUUM ENCAPSULATED DEVICES AND DAMASCENE METHOD OF MANUFACTURE 有权
    用于真空封装装置的平面微阵列和制造方法

    公开(公告)号：US20110121416A1

    公开(公告)日：2011-05-26

    申请号：US13017892

    申请日：2011-01-31

    Applicant: Emmanuel P. Quevy ,  Pezhman Monadgemi ,  Roger T. Howe

    Inventor： Emmanuel P. Quevy ,  Pezhman Monadgemi ,  Roger T. Howe

    IPC: H01L29/84 ,  H01L21/04

    CPC classification number: B81C1/00293 ,  B81B7/02 ,  B81C1/00246 ,  B81C2203/0136 ,  B81C2203/0145 ,  B81C2203/0721 ,  B81C2203/0735 ,  B81C2203/0771

    Abstract: Low temperature, multi-layered, planar microshells for encapsulation of devices such as MEMS and microelectronics. The microshells include a planar perforated pre-sealing layer, below which a non-planar sacrificial layer is accessed, and a sealing layer to close the perforation in the pre-sealing layer after the sacrificial material is removed. In an embodiment, the pre-sealing layer has perforations formed with a damascene process to be self-aligned to the chamber below the microshell. The sealing layer may include a nonhermetic layer to physically occlude the perforation and a hermetic layer over the nonhermetic occluding layer to seal the perforation. In a particular embodiment, the hermetic layer is a metal which is electrically coupled to a conductive layer adjacent to the microshell to electrically ground the microshell.

    Abstract translation: 用于MEMS和微电子等器件封装的低温多层平面微型壳体。 微壳包括平面穿孔的预密封层，在其下面接近非平面牺牲层，以及密封层，用于在去除牺牲材料之后封闭预密封层中的穿孔。 在一个实施例中，预密封层具有形成有镶嵌工艺的穿孔，以与微壳下方的腔室自对准。 密封层可以包括非密封层，以物理地封闭穿孔，并且在非密封闭塞层上方具有密封层以密封穿孔。 在特定实施例中，密封层是金属，其电耦合到与微壳相邻的导电层，以电微接地微壳。

    Mems coupler and method to form the same
    38.
    发明申请
    Mems coupler and method to form the same 有权
    Mems耦合器和方法形成相同

    公开(公告)号：US20110068422A1

    公开(公告)日：2011-03-24

    申请号：US12927312

    申请日：2010-11-10

    Applicant: Emmanuel P. Quevy ,  Roger T. Howe

    Inventor： Emmanuel P. Quevy ,  Roger T. Howe

    IPC: H01L29/66

    CPC classification number: B81C1/00039 ,  B81B2201/0271

    Abstract: A MEMS coupler and a method to form a MEMS structure having such a coupler are described. In an embodiment, a MEMS structure comprises a member and a substrate. A coupler extends through a portion of the member and connects the member with the substrate. The member is comprised of a first material and the coupler is comprised of a second material. In one embodiment, the first and second materials are substantially the same. In one embodiment, the second material is conductive and is different than the first material. In another embodiment, a method for fabricating a MEMS structure comprises first forming a member above a substrate. A coupler comprised of a conductive material is then formed to connect the member with the substrate.

    Abstract translation: 描述了MEMS耦合器和形成具有这种耦合器的MEMS结构的方法。 在一个实施例中，MEMS结构包括构件和衬底。 耦合器延伸穿过构件的一部分并将构件与衬底连接。 该构件由第一材料构成，并且该耦合器由第二材料构成。 在一个实施例中，第一和第二材料基本相同。 在一个实施例中，第二材料是导电的并且不同于第一材料。 在另一个实施例中，一种用于制造MEMS结构的方法包括首先在衬底上形成构件。 然后形成由导电材料构成的耦合器，以将该构件与衬底连接。

    Microshells for multi-level vacuum cavities
    39.
    发明授权
    Microshells for multi-level vacuum cavities 有权
    用于多层真空腔的微型壳

    公开(公告)号：US07659150B1

    公开(公告)日：2010-02-09

    申请号：US11716156

    申请日：2007-03-09

    Applicant: Pezhman Monadgemi ,  Roger T. Howe ,  Emmanuel P. Quevy

    Inventor： Pezhman Monadgemi ,  Roger T. Howe ,  Emmanuel P. Quevy

    IPC: H01L21/00

    CPC classification number: H01L23/10 ,  B81B2207/012 ,  B81C1/00293 ,  B81C2203/0136 ,  B81C2203/0145 ,  H01L23/26 ,  H01L2924/0002 ,  H01L2924/13091 ,  H01L2924/3011 ,  H01L2924/00

    Abstract: Microshells for encapsulation of devices such as MEMS and microelectronics. In an embodiment, the microshells include a planar perforated pre-sealing layer, below which a non-planar sacrificial layer is accessed, and a sealing layer to close the perforation in the pre-sealing layer after the sacrificial material is removed. The sealing layer may include a nonhermetic layer to physically occlude the perforation and a hermetic layer over the nonhermetic occluding layer to seal the perforation as a function of the dimension of the perforation to form cavities having different vacuum levels on the same substrate.

    Abstract translation: 用于封装MEMS和微电子等器件的微型外壳。 在一个实施例中，微壳包括平面穿孔的预密封层，在其下面存取非平面牺牲层，以及密封层，用于在去除牺牲材料之后封闭预密封层中的穿孔。 密封层可以包括非密封层，以物理地闭塞穿孔，并且在非密封闭塞层上方形成密封层，以密封穿孔，作为穿孔尺寸的函数，以在同一基底上形成具有不同真空度的空腔。

    Low stress thin film microshells
    40.
    发明授权
    Low stress thin film microshells 有权
    低应力薄膜微壳

    公开(公告)号：US07595209B1

    公开(公告)日：2009-09-29

    申请号：US11716233

    申请日：2007-03-09

    Applicant: Pezhman Monadgemi ,  Emmanuel P. Quevy ,  Roger T. Howe

    Inventor： Pezhman Monadgemi ,  Emmanuel P. Quevy ,  Roger T. Howe

    IPC: H01L21/56 ,  H01L21/50

    CPC classification number: B81C1/0023 ,  B81B7/0054 ,  B81C2201/0167 ,  B81C2203/0136 ,  B81C2203/0145 ,  H01L21/568 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    Abstract: Multi-layered, planar microshells having low stress for encapsulation of devices such as MEMS and microelectronics. The microshells may include a perforated pre-sealing layer, below which a sacrificial layer is accessed, and a sealing layer to close the perforation in the pre-sealing layer after the sacrificial material is removed. The sealing layer may further include a nonhermetic layer to physically occlude the perforation and a hermetic layer over the nonhermetic occluding layer to seal the perforation. The various layers may be formed employing processes having opposing stresses to tune the residual stress of the multi-layered microshell. In an embodiment, the hermetic layer is a metal which is deposited with a process tuned to impart a tensile stress to lower the residual stress in the microshell below the magnitude of cumulative stress present in sealing layer and pre-sealing layer.

    Abstract translation: 具有低应力的多层平面微壳体，用于诸如MEMS和微电子器件的封装。 微壳可以包括穿孔的预密封层，在其下方存取牺牲层，以及密封层，用于在去除牺牲材料之后封闭预密封层中的穿孔。 密封层还可以包括非密封层，以物理地封闭穿孔，并且在非密封闭塞层上方形成密封层以密封穿孔。 可以使用具有相反应力的工艺来形成各个层，以调节多层微壳的残余应力。 在一个实施例中，密封层是金属，其沉积有被调整以赋予拉伸应力的工艺，以将微壳中的残余应力降低到低于存在于密封层和预密封层中的累积应力的大小。

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