公开(公告)号：US09489985B2

公开(公告)日：2016-11-08

申请号：US13443955

申请日：2012-04-11

Applicant: Yoshihiro Machida ,  Nobuhiro Tsutsumi ,  Kouji Kamogawa

Inventor： Yoshihiro Machida ,  Nobuhiro Tsutsumi ,  Kouji Kamogawa

IPC: H04N9/80 ,  G11B27/34 ,  G06F3/0481 ,  G11B19/02 ,  G11B27/30 ,  H04N21/41 ,  H04N21/426 ,  H04N21/434 ,  H04N21/442 ,  H04N21/466

CPC classification number: H04N21/4312 ,  G06F3/0481 ,  G06F3/04847 ,  G06F3/04886 ,  G06F2203/04803 ,  G11B19/025 ,  G11B27/3027 ,  G11B27/34 ,  G11B27/36 ,  H04N21/4122 ,  H04N21/4263 ,  H04N21/434 ,  H04N21/4345 ,  H04N21/44222 ,  H04N21/466 ,  H04N21/47217

Abstract: A digital content operating apparatus, including: a communication unit which communicates with an external device which has a display for displaying the digital content; a user operation interface which receives a user operation to control the digital content which is displayed on the external device; a display which displays either a linear content operation panel or an interactive content operation panel; and a controller which controls the user operation interface corresponding to information on the digital content which is displayed on the external device; wherein either the linear content operation panel or the interactive content operation panel is displayed alternatively as the user operation interface on the display.

Abstract translation: 一种数字内容操作装置，包括：通信单元，其与具有用于显示数字内容的显示器的外部设备通信; 接收用户操作以控制显示在外部设备上的数字内容的用户操作界面; 显示线性内容操作面板或交互式内容操作面板的显示器; 以及控制器，其控制对应于在外部设备上显示的数字内容的信息的用户操作界面; 其中线性内容操作面板或交互内容操作面板作为显示器上的用户操作界面交替显示。

公开(公告)号：US08549947B2

公开(公告)日：2013-10-08

申请号：US12920646

申请日：2009-02-17

Applicant: Yoshio Iwase ,  Masahiro Machida ,  Yoshihiro Machida

Inventor： Yoshio Iwase ,  Masahiro Machida ,  Yoshihiro Machida

IPC: F16H1/06 ,  F16H1/20

CPC classification number: F16H1/163 ,  B23Q2220/004 ,  F16H55/10 ,  F16H55/24

Abstract: Provided are a ball-type speed reducer and a rotary table device that are capable of performing high-speed rotation and high-rigidity rotation and suitable for reduction in size and weight. An index table 10 includes a ball-type speed reducer 20 and a table 50 that is fixed to an upper surface of a worm wheel 30 of the ball-type speed reducer 20. When the worm gear 22 rotates as the input shaft 24 of the ball-type speed reducer 20 rotates, balls 36 made of a magnetic material move along a ball groove 26 having a spiral shape. The worm wheel 30 rotates as the balls 36 move, and the table 50 rotates. The balls 36 are attracted and held by the permanent magnet 34 on the worm wheel 30 side, so that a case for preventing the balls 36 from coming off the worm wheel 30 can be omitted, whereby the total size and weight can be reduced. Backlash is not required, so that high-speed rotation and high-rigidity rotation are possible.

Abstract translation: 提供能够进行高速旋转和高刚性旋转的球型减速器和旋转台装置，适合于减小尺寸和重量。 分度表10包括球形减速器20和固定到球型减速器20的蜗轮30的上表面的工作台50.当蜗轮22作为输入轴24旋转时， 球型减速器20旋转，由磁性材料制成的球36沿着具有螺旋形状的球槽26移动。 蜗轮30随着滚珠36移动而旋转，并且台子50旋转。 滚珠36被蜗轮30侧的永久磁铁34吸引并保持，从而可以省略防止滚珠36从蜗轮30脱落的壳体，能够减小总尺寸和重量。 不需要间隙，因此可以进行高速旋转和高刚性旋转。

公开(公告)号：US08419325B2

公开(公告)日：2013-04-16

申请号：US11794378

申请日：2006-09-15

Applicant: Ichiro Kitaura ,  Yoshihiro Machida

Inventor： Ichiro Kitaura ,  Yoshihiro Machida

IPC: B23C5/26

CPC classification number: B23B31/261 ,  B23B2260/02 ,  Y10T279/3481 ,  Y10T408/95 ,  Y10T409/309464

Abstract: A tool unclamping device is a device capable of unclamping a tool clamped to a spindle of a machine tool, and comprises a casing, an output shaft set on this casing and capable of outputting power necessary for unclamping the tool, a motor serving as a power source capable of supplying power for driving the output shaft, a power transmission mechanism transmitting the power from the motor to the output shaft and a gas cylinder serving as an auxiliary power source capable of supplying auxiliary power to this power transmission mechanism.

Abstract translation: 工具松开装置是能够松开夹在机床主轴上的工具的装置，并且包括壳体，设置在该壳体上的输出轴，并且能够输出用于松开工具所需的动力，作为动力的电动机 能够供给驱动输出轴的动力源，将电动机从电动机传递到输出轴的动力传递机构和能够向该动力传递机构供给辅助动力的辅助动力源的气缸。

公开(公告)号：US08222747B2

公开(公告)日：2012-07-17

申请号：US13032975

申请日：2011-02-23

Applicant: Yoshihiro Machida

Inventor： Yoshihiro Machida

IPC: H01L23/48

CPC classification number: H05K1/186 ,  H01L23/13 ,  H01L23/49822 ,  H01L23/5389 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H05K3/4602 ,  H05K2201/09845 ,  H05K2203/049 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401

Abstract: A multilayer wiring substrate mounted with an electronic component includes an electronic component, a core material layer having a first opening for accommodating the electronic component, a resin layer which is formed on one surface of the core material layer and which has a second opening greater than the first opening, a supporting layer which is formed on the other surface of the core material layer and which supports the electronic component, a plurality of connection conductor sections which are provided around the first opening and within the second opening on the one surface of the core material layer, bonding wires for electrically connecting the electronic component to the connection conductor sections, and a sealing resin filled into the first and second openings in order to seal the electronic component and the bonding wires.

Abstract translation: 安装有电子部件的多层布线基板包括电子部件，具有容纳电子部件的第一开口的芯材层，形成在芯材层的一个面上的树脂层，其具有大于 所述第一开口，形成在所述芯材料层的另一个表面上并且支撑所述电子部件的支撑层，多个连接导体部，所述多个连接导体部设置在所述第一开口的周围，并且位于所述第一开口的一个表面上 芯材料层，用于将电子部件电连接到连接导体部分的接合线以及填充到第一和第二开口中的密封树脂，以密封电子部件和接合线。

公开(公告)号：US08096049B2

公开(公告)日：2012-01-17

申请号：US12929090

申请日：2010-12-30

Applicant: Tetsuya Koyama ,  Tsuyoshi Kobayashi ,  Hiroyuki Kato ,  Yoshihiro Machida

Inventor： Tetsuya Koyama ,  Tsuyoshi Kobayashi ,  Hiroyuki Kato ,  Yoshihiro Machida

IPC: H01K3/00

CPC classification number: H05K3/4614 ,  H05K3/462 ,  H05K3/4647 ,  H05K2203/061 ,  H05K2203/0733 ,  H05K2203/1327 ,  H05K2203/1476 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49146 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/4916 ,  Y10T29/49165

Abstract: First, a unilayer wiring board is fabricated, which has wiring layers formed in desired shapes on both sides of an insulating base member; and a metal bump formed on the wiring layer on one side of the insulating base member. Then, a desired number of unilayer boards are prepared and stacked up. On that case, the board disposed in the uppermost layer is prepared without having a metal bump. The boards are positioned and stacked up in such a manner that a metal bump of one of adjacent boards is connected to a corresponding wiring layer of the other board. Thereafter, resin is filled into gaps between the stacked boards, and insulating layers are formed on both sides of a multilayer board obtained through the above steps, in such a manner as to cover the entire surface except pad areas defined at predetermined positions on the wiring layers.

Abstract translation: 首先，制造单层布线板，其具有在绝缘基材的两侧形成为所需形状的布线层; 以及在所述绝缘基体的一侧上的所述布线层上形成的金属凸块。 然后，准备并堆叠所需数量的单层板。 在这种情况下，准备设置在最上层的板，而不具有金属凸块。 这些板被定位和堆叠，使得相邻板中的一个的金属凸块连接到另一个板的对应的布线层。 此后，将树脂填充到堆叠板之间的间隙中，并且在通过上述步骤获得的多层板的两侧上形成绝缘层，以覆盖除了在布线上的预定位置限定的焊盘区域之外的整个表面 层。

公开(公告)号：US07994431B2

公开(公告)日：2011-08-09

申请号：US11907179

申请日：2007-10-10

Applicant: Takaharu Yamano ,  Yoshihiro Machida

Inventor： Takaharu Yamano ,  Yoshihiro Machida

IPC: H05K1/16

CPC classification number: H05K1/186 ,  H01L23/5384 ,  H01L23/5389 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16237 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15313 ,  H01L2924/3511 ,  H05K3/4644 ,  H05K2201/0191 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2203/0733 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A substrate with built-in electronic components includes a substrate on which a first conductive pattern is formed; an electronic component mounted on the substrate; an insulting layer which is formed by stacking a plurality of resin layers including indifferent additive ratios an additive material for adjusting hardness; a second conductive pattern formed on the insulating layer; and a conductive post for connecting the first conductive pattern to the second conductive pattern.

Abstract translation: 具有内置电子部件的基板包括其上形成有第一导电图案的基板; 安装在所述基板上的电子部件; 绝缘层，其通过堆叠包括无差异添加剂比例的多个树脂层形成，用于调节硬度的添加剂材料; 形成在所述绝缘层上的第二导电图案; 以及用于将第一导电图案连接到第二导电图案的导电柱。

公开(公告)号：US07936061B2

公开(公告)日：2011-05-03

申请号：US12485601

申请日：2009-06-16

Applicant: Yoshihiro Machida

Inventor： Yoshihiro Machida

IPC: H01L21/00

CPC classification number: H01L21/563 ,  H01L21/4857 ,  H01L23/3128 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device includes: a first insulating layer having an opening therethrough; a first wiring pattern disposed on the first insulating layer; an external connection terminal provided on a portion of the first wiring pattern exposed from the opening; a second insulating layer which covers the first wiring pattern and having via holes therethrough; a second wiring pattern disposed within the second insulating layer and electrically connected to the first wiring pattern via a conductive material filled in at least one of the via holes; a semiconductor element having an electrode thereon and mounted on the second insulating layer to be electrically connected to the first wiring pattern through the electrode disposed in at least one of the via holes; an underfill resin filled between the semiconductor element and the second insulating layer; and a sealing resin portion which seals the semiconductor element.

Abstract translation: 半导体器件包括：具有穿过其中的开口的第一绝缘层; 布置在所述第一绝缘层上的第一布线图案; 设置在从所述开口露出的所述第一布线图案的一部分上的外部连接端子; 第二绝缘层，其覆盖所述第一布线图案并且具有穿过其的通孔; 第二布线图案，设置在所述第二绝缘层内并且经由填充在至少一个所述通孔中的导电材料电连接到所述第一布线图案; 半导体元件，其上具有电极，并且安装在第二绝缘层上，以通过布置在至少一个通孔中的电极电连接到第一布线图案; 填充在所述半导体元件和所述第二绝缘层之间的底部填充树脂; 以及密封半导体元件的密封树脂部分。

公开(公告)号：US07893524B2

公开(公告)日：2011-02-22

申请号：US12263584

申请日：2008-11-03

Applicant: Masahiro Sunohara ,  Yoshihiro Machida

Inventor： Masahiro Sunohara ,  Yoshihiro Machida

IPC: H01L21/00 ,  H01L21/44 ,  H01L23/02

CPC classification number: H01L23/49811 ,  H01L21/4846 ,  H01L23/42 ,  H01L23/49822 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/01019 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/16152 ,  H05K1/0271 ,  H05K1/111 ,  H05K3/4092 ,  H05K3/4644 ,  H05K2201/0133 ,  H05K2201/0187 ,  H05K2201/0397 ,  H05K2201/09036 ,  H05K2201/10674 ,  H01L2924/00

Abstract: In a wiring substrate of a semiconductor device, a hollow portion is provided under a pad wiring portion including a connection pad, and thus a wiring layer has a cantilever structure in which the pad wiring portion is formed as an aerial wiring, and a semiconductor chip is flip-chip connected to the connection pad. The pad wiring portion including the connection pad is formed on a sacrifice layer which is filled in a recess portion in an interlayer insulating layer of the wiring substrate, then the semiconductor chip is flip-chip connected to the connection pad, and then the hollow portion is provided by removing the sacrifice layer.

Abstract translation: 在半导体器件的布线基板中，在包括连接焊盘的焊盘布线部分的下方设置中空部，由此布线层具有悬臂结构，其中焊盘布线部分形成为架空布线，半导体芯片 倒装芯片连接到连接板。 包括连接焊盘的焊盘布线部分形成在填充在布线基板的层间绝缘层的凹部中的牺牲层上，然后将半导体芯片倒装芯片连接到连接焊盘，然后将中空部分 通过去除牺牲层来提供。

公开(公告)号：US20090115073A1

公开(公告)日：2009-05-07

申请号：US12263584

申请日：2008-11-03

Applicant: Masahiro SUNOHARA ,  Yoshihiro Machida

Inventor： Masahiro SUNOHARA ,  Yoshihiro Machida

IPC: H01L23/52 ,  H01L21/00

CPC classification number: H01L23/49811 ,  H01L21/4846 ,  H01L23/42 ,  H01L23/49822 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/01019 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/16152 ,  H05K1/0271 ,  H05K1/111 ,  H05K3/4092 ,  H05K3/4644 ,  H05K2201/0133 ,  H05K2201/0187 ,  H05K2201/0397 ,  H05K2201/09036 ,  H05K2201/10674 ,  H01L2924/00

Abstract: In a wiring substrate of a semiconductor device, a hollow portion is provided under a pad wiring portion including a connection pad, and thus a wiring layer has a cantilever structure in which the pad wiring portion is formed as an aerial wiring, and a semiconductor chip is flip-chip connected to the connection pad. The pad wiring portion including the connection pad is formed on a sacrifice layer which is filled in a recess portion in an interlayer insulating layer of the wiring substrate, then the semiconductor chip is flip-chip connected to the connection pad, and then the hollow portion is provided by removing the sacrifice layer.

Abstract translation: 在半导体器件的布线基板中，在包括连接焊盘的焊盘布线部分的下方设置中空部，由此布线层具有悬臂结构，其中焊盘布线部分形成为架空布线，半导体芯片 倒装芯片连接到连接板。 包括连接焊盘的焊盘布线部分形成在填充在布线基板的层间绝缘层的凹部中的牺牲层上，然后将半导体芯片倒装芯片连接到连接焊盘，然后将中空部分 通过去除牺牲层来提供。

公开(公告)号：US20090001569A1

公开(公告)日：2009-01-01

申请号：US11870743

申请日：2007-10-11

Applicant: Yoshihiro Machida ,  Takaharu Yamano

Inventor： Yoshihiro Machida ,  Takaharu Yamano

IPC: H01L21/60 ,  H01L23/498

CPC classification number: H01L23/3114 ,  H01L21/6835 ,  H01L23/485 ,  H01L23/525 ,  H01L24/11 ,  H01L24/12 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2221/68377 ,  H01L2224/0231 ,  H01L2224/02319 ,  H01L2224/02333 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01088 ,  H01L2924/014

Abstract: A semiconductor chip is characterized by a structure including a semiconductor chip on which electrode pads are formed, bumps which are formed on the respective electrode pads and which have projection sections, an insulating layer formed on the semiconductor chip, and a conductive pattern to be connected to the bumps, wherein extremities of the projection sections are inserted into the conductive pattern and the inserted extremities are flattened.

Abstract translation: 半导体芯片的特征在于包括其上形成有电极焊盘的半导体芯片的结构，形成在各个电极焊盘上的凸起，并且具有突出部分，形成在半导体芯片上的绝缘层和要连接的导电图案 到凸块，其中突出部分的末端插入到导电图案中，并且插入的末端被平坦化。