公开(公告)号：US07805835B2

公开(公告)日：2010-10-05

申请号：US12128726

申请日：2008-05-29

Applicant: Hsien-Ming Dai ,  Jen-Fang Chang ,  Jun-Chung Hsu

Inventor： Hsien-Ming Dai ,  Jen-Fang Chang ,  Jun-Chung Hsu

IPC: H05K3/00 ,  H01L21/00

CPC classification number: H05K3/3452 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49894 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/01078 ,  H01L2924/01079 ,  H05K3/305 ,  H05K3/381 ,  H05K2201/10674 ,  H05K2201/10977 ,  H05K2203/1152 ,  H05K2203/1173 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49149 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method for selectively processing a surface tension of a solder mask layer in a circuit board is provided. The method conducts surface tension processing to the flip-chip area and the non-flip-chip area of the solder mask layer in the circuit board. Therefore, the underfill used in packaging configures relative contact angles at the flip-chip area and the non-flip-chip area of the solder mask layer, respectively. In such a way, the present invention is adapted to solve the difficulties of the underfill void bulb and the overflowing contamination at the same time.

Abstract translation: 提供一种用于选择性地处理电路板中的焊料掩模层的表面张力的方法。 该方法对电路板中的焊料掩模层的倒装芯片区域和非倒装芯片区域进行表面张力处理。 因此，封装中使用的底部填充物分别在焊接掩模层的倒装芯片区域和非倒装芯片区域分别形成相对接触角。 以这种方式，本发明适用于同时解决底部填充空隙的困难和溢出的污染。

公开(公告)号：US07768131B1

公开(公告)日：2010-08-03

申请号：US12493171

申请日：2009-06-27

Applicant: Jun-Chung Hsu ,  Chen-Lin Li

Inventor： Jun-Chung Hsu ,  Chen-Lin Li

IPC: H01L23/48

CPC classification number: H05K3/341 ,  H01L23/49811 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/10175 ,  H01L2224/16 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01078 ,  H05K3/3436 ,  H05K2201/0373 ,  H05K2201/09745 ,  H05K2201/099 ,  Y02P70/613 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A package structure preventing solder overflow on substrate solder pads includes a plurality of die pins, a plurality of solders and a plurality of substrate solder pads. The die pins are located under a die. The substrate solder pads are formed on an upper surface of a substrate by copper plating or etching. Each of the substrate solder pads has at least one solder pad connection point. The solders connect the die pins with the corresponding solder pad connection points, respectively. Each of the solder pad connection points has a pair of solder pad ridges or a pair of solder pad grooves. The solder pad ridges and the solder pad grooves filled with the solder or a resin can prevent the solder overflow problem.

Abstract translation: 防止衬底焊盘上的焊料溢出的封装结构包括多个管芯引脚，多个焊料和多个衬底焊盘。 模具销位于模具下方。 通过镀铜或蚀刻在衬底的上表面上形成衬底焊盘。 每个衬底焊盘具有至少一个焊盘连接点。 焊料将管芯引脚分别与相应的焊盘连接点相连。 每个焊盘连接点具有一对焊盘凸脊或一对焊盘凹槽。 焊料焊盘脊和填充有焊料或树脂的焊盘凹槽可以防止焊料溢出问题。

公开(公告)号：US11044806B2

公开(公告)日：2021-06-22

申请号：US16718100

申请日：2019-12-17

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Chin-Kuan Liu ,  Chao-Lung Wang ,  Shuo-Hsun Chang ,  Yu-Te Lu ,  Chin-Hsi Chang

IPC: H05K1/02 ,  H05K1/09 ,  H05K3/46 ,  H05K3/06 ,  H05K3/24

Abstract: A multi-layer circuit structure is disposed on the delivery loading plate through the bottom-layer circuit structure, the delivery loading plate exposes the conductive corrosion-barrier layer, and the top-layer circuit of the multi-layer circuit structure is electrically connected to the conductive corrosion-barrier layer through the bottom-layer circuit and the electrical connection layer. Therefore, before the multi-layer circuit board is delivered to the assembly company or before the multi-layer circuit board is packaged with chips, an electrical testing can be applied to the multi-layer circuit board.

公开(公告)号：US10440836B2

公开(公告)日：2019-10-08

申请号：US15138261

申请日：2016-04-26

Applicant: Kinsus Interconnect Technology Corp.

Inventor： Ting-Hao Lin ,  Chiao-Cheng Chang ,  Yi-Nong Lin

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/42 ,  H05K3/00 ,  H05K3/46

Abstract: Provided is a double layer circuit board and a manufacturing method thereof. The double layer circuit board comprises a substrate, a first circuit layer formed on a first surface of the substrate, a second circuit layer formed on a second surface of the substrate, and at least one connecting pillar formed in and covered by the substrate. Each one of the at least one connecting pillar includes a first end connected to the first circuit layer and a second end connected to the second circuit layer. A terminal area of the second end is greater than a terminal area of the first end. Therefore, the second circuit layer is firmly connected to the first circuit layer through the at least one connecting pillar. A yield rate of the double layer circuit board may be increased.

公开(公告)号：US10334719B2

公开(公告)日：2019-06-25

申请号：US15826692

申请日：2017-11-30

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Chin-Kuan Liu ,  Chao-Lung Wang ,  Shuo-Hsun Chang ,  Yu-Te Lu ,  Chin-Hsi Chang

IPC: H05K1/02 ,  H05K1/09 ,  H05K3/46 ,  H05K3/06

Abstract: A multi-layer circuit board capable of being applied with electrical testing includes a patterned metal-interface layer, a metallic delivery loading plate, an electrical connection layer, a conductive corrosion-barrier layer, a bottom dielectric layer, and a multi-layer circuit structure. The multi-layer circuit structure is disposed on the delivery loading plate through the bottom dielectric layer. The top-layer circuit of the multi-layer circuit structure is electrically connected to the conductive corrosion-barrier layer through the bottom-layer circuit and the electrical connection layer. The delivery loading plate and the patterned metal-interface layer expose the conductive corrosion-barrier layer. Therefore, before the multi-layer circuit board is packaged, an electrical testing can be applied to the multi-layer circuit board to check if it can be operated normally. Hence, costs for figuring out reasons of the unqualified electronic component can be reduced, and responsibilities for the unqualified electrical testing result of the electronic component can be clarified.

公开(公告)号：US10256028B2

公开(公告)日：2019-04-09

申请号：US15086333

申请日：2016-03-31

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Ting-Hao Lin ,  Chiao-Cheng Chang ,  Yi-Nong Lin

IPC: H01F27/28 ,  H05K1/03 ,  H05K1/11 ,  H05K1/16 ,  H05K3/46

Abstract: A buildup board structure incorporating magnetic induction coils and flexible boards is disclosed. The buildup board structure includes at least one first, second and third buildup bodies modular and stackable. Any two adjacent buildup bodies are separated by a covering layer provided with a central hole for electrical insulation. All central holes are aligned. Each buildup body includes a plurality of flexible boards, and each flexible board is embedded with a plurality of magnetic induction coils surrounding the corresponding central hole and connected through connection pads. The first, second and third buildup bodies are easily laminated in any order by any number as desired such that the effect of magnetic induction provided by the magnetic induction coils embedded in the buildup board structure are addable to greatly enhance the overall effect of magnetic induction.

公开(公告)号：US10039185B2

公开(公告)日：2018-07-31

申请号：US15130724

申请日：2016-04-15

Applicant: Kinsus Interconnect Technology Corp.

Inventor： Ting-Hao Lin ,  Chiao-Cheng Chang ,  Yi-Nong Lin

IPC: H01K3/10 ,  H05K1/11 ,  H05K3/18 ,  H05K3/42 ,  H05K3/00 ,  H05K3/46

CPC classification number: H05K1/115 ,  H05K1/113 ,  H05K3/0047 ,  H05K3/0079 ,  H05K3/0094 ,  H05K3/108 ,  H05K3/18 ,  H05K3/429 ,  H05K3/4644 ,  H05K3/4647 ,  H05K2203/054 ,  Y10T29/49165

Abstract: Provided is a landless multilayer circuit board and a manufacturing method thereof. The manufacturing method includes steps of forming a first circuit on a first substrate, patterning a photoresist layer to form at least one via between the first circuit and a second circuit, forming at least one connecting pillar in the at least one via, removing the photoresist layer, forming a second substrate to cover the at least one connect pillar, and forming the second circuit on the second substrate. The second circuit is connected to the first circuit through the at least one connecting pillar. When the second circuit is formed, the at least one via does not need to be filled, thereby making the second circuit flat.

公开(公告)号：US09901016B1

公开(公告)日：2018-02-20

申请号：US15488133

申请日：2017-04-14

Applicant: Kinsus Interconnect Technology Corp.

Inventor： Ting-Hao Lin ,  Chiao-Cheng Chang ,  Yung-Lin Chia

IPC: H05K9/00

CPC classification number: H05K9/0037 ,  H05K9/003

Abstract: An EMI shielding device is provided. A first shielding layer is formed on a first surface of a first substrate, and a first through hole is formed through the first substrate. A second substrate is mounted in an opening of the first through hole, and a second shielding layer is formed on a surface of the second substrate. A conductive paste is mounted between the first substrate and the at least one second substrate to electrically connected the first shielding layer and the second shielding layer. A protective layer, an antirust layer, and a shielding layer are sequentially mounted on the conductive paste. The EMI shielding device is mounted on a printed circuit board (PCB) by Surface Mount Technology. Therefore, the EMI shielding device may be firmly mounted on the PCB, and there is not any narrow gap that may leak electromagnetic radiation.

公开(公告)号：US09406641B2

公开(公告)日：2016-08-02

申请号：US13938335

申请日：2013-07-10

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Ting-Hao Lin ,  Yi-Fan Kao ,  Shuo-Hsun Chang ,  Yu-Te Lu ,  Kuo-Chun Huang

IPC: H01L23/00 ,  H01L23/31 ,  H05K3/46 ,  H01L23/498 ,  H05K1/02 ,  H05K1/18 ,  H01L25/10

CPC classification number: H01L24/81 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/562 ,  H01L24/16 ,  H01L25/105 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/18161 ,  H01L2924/3511 ,  H05K1/0206 ,  H05K1/0271 ,  H05K1/183 ,  H05K3/4697 ,  H05K2201/10378 ,  H05K2201/10734 ,  H05K2203/061 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A compound carrier board structure of Flip-Chip Chip-Scale Package and manufacturing method thereof provides a baseplate having a flip region with a through-opening and bonding to a Non-conductive Film to bond to a carrier board in order to form a compound carrier board structure. The baseplate is constructed with a low Thermal Expansion Coefficient material.

Abstract translation: Flip-Chip Chip-Scale封装的复合载体板结构及其制造方法提供了一种具有通孔的翻转区和与非导电膜结合以结合到载体板以形成化合物载体的底板 板结构。 底板由低热膨胀系数材料构成。

公开(公告)号：US09095084B2

公开(公告)日：2015-07-28

申请号：US13853303

申请日：2013-03-29

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Ting-Hao Lin ,  Yu-Te Lu ,  De-Hao Lu

IPC: H05K1/00 ,  H05K1/09 ,  H05K1/03 ,  H05K1/11 ,  H05K3/46 ,  H05K3/38

CPC classification number: H05K3/4647 ,  H05K1/0366 ,  H05K3/38

Abstract: A stacked multilayer structure, including a first circuit layer having bumps, a plastic film stacked on the first circuit layer to fill up the space among the bumps so as to form a co-plane, and a second circuit layer formed on the co-plane and connected to the first circuit layer. The plastic film includes a glass fiber layer which is embedded and not exposed.

Abstract translation: 一种堆叠多层结构，包括具有凸起的第一电路层，堆叠在第一电路层上以填充凸块之间的空间以形成共面的塑料膜，以及形成在共面上的第二电路层 并连接到第一电路层。 该塑料膜包括嵌入并不暴露的玻璃纤维层。