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    Method for manufacturing floating structure of microelectromechanical system
    31.
    发明授权
    Method for manufacturing floating structure of microelectromechanical system 有权
    微机电系统浮动结构制造方法

    公开(公告)号：US07879629B2

    公开(公告)日：2011-02-01

    申请号：US11927810

    申请日：2007-10-30

    Applicant: Sang-Choon Ko ,  Chi-Hoon Jun ,  Hyeon-Bong Pyo ,  Seon-Hee Park

    Inventor： Sang-Choon Ko ,  Chi-Hoon Jun ,  Hyeon-Bong Pyo ,  Seon-Hee Park

    IPC: H01L21/00 ,  H01L21/311

    CPC classification number: B81C1/00801 ,  B81C2201/0133 ,  B81C2201/0136

    Abstract: Provided is a method for manufacturing a floating structure of a MEMS. The method for manufacturing a floating structure of a microelectromechanical system (MEMS), comprising the steps of: a) forming a sacrificial layer including a thin layer pattern doped with impurities on a substrate; b) forming a support layer on the sacrificial layer; c) forming a structure to be floated on the support layer by using a subsequent process; d) forming an etch hole exposing both side portions of the thin layer pattern; and e) removing the sacrificial layer through the etch hole to form an air gap between the support layer and the substrate.

    Abstract translation: 提供了一种用于制造MEMS的浮动结构的方法。 一种用于制造微机电系统（MEMS）的浮动结构的方法，包括以下步骤：a）在衬底上形成包含掺杂有杂质的薄层图案的牺牲层; b）在牺牲层上形成支撑层; c）通过使用随后的方法形成浮在支撑层上的结构; d）形成暴露薄层图案的两侧部分的蚀刻孔; 以及e）通过所述蚀刻孔去除所述牺牲层，以在所述支撑层和所述基底之间形成气隙。

    METHOD OF FABRICATING A MEMS/NEMS ELECTROMECHANICAL COMPONENT
    32.
    发明申请
    METHOD OF FABRICATING A MEMS/NEMS ELECTROMECHANICAL COMPONENT 有权
    制造MEMS / NEMS电子元件的方法

    公开(公告)号：US20100029031A1

    公开(公告)日：2010-02-04

    申请号：US12488898

    申请日：2009-06-22

    Applicant: François Perruchot ,  Bernard Diem ,  Vincent Larrey ,  Laurent Clavelier ,  Emmanuel Defay

    Inventor： François Perruchot ,  Bernard Diem ,  Vincent Larrey ,  Laurent Clavelier ,  Emmanuel Defay

    IPC: H01L21/18

    CPC classification number: B81C1/00507 ,  B81B2201/0271 ,  B81C2201/0115 ,  B81C2201/0136 ,  B81C2201/0177 ,  B81C2203/0136 ,  B81C2203/0145 ,  H03H3/0072 ,  H03H9/175 ,  H03H9/2436 ,  Y10S438/933

    Abstract: The invention relates to a method of fabricating and electromechanical device on at least one substrate, the device including at least one active element and wherein the method comprises: a) making a heterogeneous substrate comprising a first portion, an interface layer, and a second portion, the first portion including one or more buried zones sandwiched between first and second regions formed in a first monocrystalline material, the first region extending to the surface of the first portion, and the second region extending to the interface layer, at least one said buried zone being made at least in part out of a second monocrystalline material so as to make it selectively attackable relative to the first and second regions; b) making openings from the surface of the first portion and through the first region, which openings open out to at least one said buried zone; and c) etching at least part of at least one buried zone to form at least one cavity so as to define at least one active element that is at least a portion of the second region between a said cavity and said interface layer; and wherein the first and second portions of the substrate are constituted respectively from first and second substrates that are assembled together by bonding, at least one of them including at least one said interface layer over at least a fraction of its surface.

    Abstract translation: 本发明涉及在至少一个基板上制造和机电装置的方法，所述装置包括至少一个有源元件，并且其中所述方法包括：a）制造包含第一部分，界面层和第二部分 ，所述第一部分包括被夹在形成于第一单晶材料中的第一和第二区域之间的一个或多个掩埋区域，所述第一区域延伸到所述第一部分的表面，并且所述第二区域延伸到所述界面层，所述第二区域延伸至所述界面层， 区域至少部分地由第二单晶材料制成，以使其相对于第一和第二区域选择性地被破坏; b）从所述第一部分的表面和所述第一区域制造开口，所述第一区域开放到至少一个所述掩埋区域; 以及c）蚀刻至少一个掩埋区的至少一部分以形成至少一个空腔，以便限定至少一个有源元件，所述至少一个有源元件是所述空腔和所述界面层之间的所述第二区域的至少一部分; 并且其中所述基底的第一和第二部分分别由通过粘合而组装在一起的第一和第二基底构成，其中至少一个在其表面的至少一部分上包括至少一个所述界面层。

    Boron doped shell for MEMS device
    33.
    发明授权
    Boron doped shell for MEMS device 有权
    用于MEMS器件的硼掺杂外壳

    公开(公告)号：US07563720B2

    公开(公告)日：2009-07-21

    申请号：US11781470

    申请日：2007-07-23

    Applicant: James F. Detry

    Inventor： James F. Detry

    IPC: H01L21/311

    CPC classification number: B81C1/00595 ,  B81C1/00365 ,  B81C2201/0136 ,  B81C2201/0167 ,  B81C2203/031

    Abstract: A wafer for use in a MEMS device having two doped layers surrounding an undoped layer of silicon is described. By providing two doped layers around an undoped core, the stress in the lattice structure of the silicon is reduced as compared to a solidly doped layer. Thus, problems associated with warping and bowing are reduced. The wafer may have a pattered oxide layer to pattern the deep reactive ion etch. A first deep reactive ion etch creates trenches in the layers. The walls of the trenches are doped with boron atoms. A second deep reactive ion etch removes the bottom walls of the trenches. The wafer is separated from the silicon substrate and bonded to at least one glass wafer.

    Abstract translation: 描述了一种用于具有围绕未掺杂硅层的两个掺杂层的MEMS器件的晶片。 通过在未掺杂的芯周围提供两个掺杂层，与固体掺杂层相比，硅的晶格结构中的应力降低。 因此，与翘曲和弯曲相关的问题减少。 晶片可以具有图案化的氧化物层以对深层反应离子蚀刻进行图案化。 第一深反应离子蚀刻在层中产生沟槽。 沟槽的壁掺杂有硼原子。 第二次深反应离子蚀刻去除沟槽的底壁。 将晶片与硅衬底分离并结合至至少一个玻璃晶片。

    SINGLE SOI WAFER ACCELEROMETER FABRICATION PROCESS
    34.
    发明申请
    SINGLE SOI WAFER ACCELEROMETER FABRICATION PROCESS 失效
    单晶硅片加速度计制造工艺

    公开(公告)号：US20090176370A1

    公开(公告)日：2009-07-09

    申请号：US11969505

    申请日：2008-01-04

    Applicant: Lianzhong Yu

    Inventor： Lianzhong Yu

    IPC: H01L21/306

    CPC classification number: B81C1/00182 ,  B81B2201/0235 ,  B81C2201/0136

    Abstract: Methods for producing a MEMS device from a single silicon-on-insulator (SOI) wafer. An SOI wafer includes a silicon (Si) handle layer, a Si mechanism layer and an insulator layer located between the Si handle and Si mechanism layers. An example method includes etching active components from the Si mechanism layer. Then, the exposed surfaces of the Si mechanism layer is doped with boron. Next, portions of the insulator layer proximate to the etched active components of the Si mechanism layer are removed and the Si handle layer is etched proximate to the etched active components.

    Abstract translation: 从单个绝缘体上硅（SOI）晶片制造MEMS器件的方法。 SOI晶片包括硅（Si）手柄层，Si机构层和位于Si手柄和Si机构层之间的绝缘体层。 示例性方法包括从Si机理层蚀刻活性组分。 然后，Si机理层的暴露表面掺杂有硼。 接下来，去除邻近Si机理层的蚀刻的有源部件的绝缘体层的部分，并且蚀刻附近的Si处理层。

    BORON DOPED SHELL FOR MEMS DEVICE
    36.
    发明申请
    BORON DOPED SHELL FOR MEMS DEVICE 有权
    用于MEMS器件的BORON DOPED SHELL

    公开(公告)号：US20090026559A1

    公开(公告)日：2009-01-29

    申请号：US11781470

    申请日：2007-07-23

    Applicant: James F. Detry

    Inventor： James F. Detry

    IPC: H01L29/84 ,  H01L21/20

    CPC classification number: B81C1/00595 ,  B81C1/00365 ,  B81C2201/0136 ,  B81C2201/0167 ,  B81C2203/031

    Abstract: A wafer for use in a MEMS device having two doped layers surrounding an undoped layer of silicon is described. By providing two doped layers around an undoped core, the stress in the lattice structure of the silicon is reduced as compared to a solidly doped layer. Thus, problems associated with warping and bowing are reduced. The wafer may have a pattered oxide layer to pattern the deep reactive ion etch. A first deep reactive ion etch creates trenches in the layers. The walls of the trenches are doped with boron atoms. A second deep reactive ion etch removes the bottom walls of the trenches. The wafer is separated from the silicon substrate and bonded to at least one glass wafer.

    Abstract translation: 描述了一种用于具有围绕未掺杂硅层的两个掺杂层的MEMS器件的晶片。 通过在未掺杂的芯周围提供两个掺杂层，与固体掺杂层相比，硅的晶格结构中的应力降低。 因此，与翘曲和弯曲相关的问题减少。 晶片可以具有图案化的氧化物层以对深层反应离子蚀刻进行图案化。 第一深反应离子蚀刻在层中产生沟槽。 沟槽的壁掺杂有硼原子。 第二次深反应离子蚀刻去除沟槽的底壁。 将晶片与硅衬底分离并结合至至少一个玻璃晶片。

    METHOD FOR MANUFACTURING FLOATING STRUCTURE OF MICROELECTROMECHANICAL SYSTEM
    37.
    发明申请
    METHOD FOR MANUFACTURING FLOATING STRUCTURE OF MICROELECTROMECHANICAL SYSTEM 有权
    微电子系统浮动结构的制造方法

    公开(公告)号：US20080233752A1

    公开(公告)日：2008-09-25

    申请号：US11927810

    申请日：2007-10-30

    Applicant: Sang-Choon KO ,  Chi-Hoon JUN ,  Hyeon-Bong PYO ,  Seon-Hee PARK

    Inventor： Sang-Choon KO ,  Chi-Hoon JUN ,  Hyeon-Bong PYO ,  Seon-Hee PARK

    IPC: H01L21/306

    CPC classification number: B81C1/00801 ,  B81C2201/0133 ,  B81C2201/0136

    Abstract: Provided is a method for manufacturing a floating structure of a MEMS. The method for manufacturing a floating structure of a microelectromechanical system (MEMS), comprising the steps of: a) forming a sacrificial layer including a thin layer pattern doped with impurities on a substrate; b) forming a support layer on the sacrificial layer; c) forming a structure to be floated on the support layer by using a subsequent process; d) forming an etch hole exposing both side portions of the thin layer pattern; and e) removing the sacrificial layer through the etch hole to form an air gap between the support layer and the substrate.

    Abstract translation: 提供了一种用于制造MEMS的浮动结构的方法。 一种用于制造微机电系统（MEMS）的浮动结构的方法，包括以下步骤：a）在衬底上形成包含掺杂有杂质的薄层图案的牺牲层; b）在牺牲层上形成支撑层; c）通过使用随后的方法形成浮在支撑层上的结构; d）形成暴露薄层图案的两侧部分的蚀刻孔; 以及e）通过所述蚀刻孔去除所述牺牲层，以在所述支撑层和所述基底之间形成气隙。

    Method of producing semiconductor device
    39.
    发明申请
    Method of producing semiconductor device 有权
    半导体器件的制造方法

    公开(公告)号：US20060141398A1

    公开(公告)日：2006-06-29

    申请号：US11276320

    申请日：2006-02-24

    Applicant: Noriyuki Shimoji ,  Masaki Takaoka

    Inventor： Noriyuki Shimoji ,  Masaki Takaoka

    IPC: G03F7/00

    CPC classification number: F04B43/043 ,  B81B2203/0353 ,  B81C1/00626 ,  B81C2201/0136 ,  H01L29/0657

    Abstract: A method of producing a semiconductor device is disclosed, in which a through hole is formed in the upper surface of a semiconductor substrate from the lower surface thereof, and an opening of a desired size is formed in a desired position on the upper surface of the substrate. A guide that functions as an etching stopper is formed in the semiconductor substrate. An opening having a width W2 is formed in the guide. The opening faces an opening in a mask used in the formation of a through hole, and the width W2 thereof is narrower than a width W4 of the opening in the mask. The direction in which etching progresses is controlled by the opening formed in the guide as etching is conducted from a lower surface of the substrate to an upper surface of the substrate, and thus deviations in the width W1 and position of an opening in the upper surface of the substrate can be controlled.

    Abstract translation: 公开了一种制造半导体器件的方法，其中在半导体衬底的上表面中形成有从其下表面的通孔，并且所需尺寸的开口形成在所述半导体衬底的上表面上的期望位置 基质。 在半导体衬底中形成用作蚀刻阻挡层的引导件。 在导向件中形成宽度为W 2的开口。 开口面向形成通孔所使用的掩模中的开口，其宽度W 2比掩模中的开口的宽度W 4窄。 蚀刻进行的方向由蚀刻形成在导向器中的开口控制，从基板的下表面传导到基板的上表面，因此宽度W 1和上部开口的位置的偏差 可以控制基板的表面。

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