公开(公告)号：US20150263746A1

公开(公告)日：2015-09-17

申请号：US14657728

申请日：2015-03-13

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Kei SHIRAISHI ,  Masanori FURUTA ,  Junya MATSUNO ,  Tetsuro ITAKURA

IPC: H03M1/08 ,  H03M1/00 ,  H03M1/66

CPC classification number: H03M1/0836 ,  H03M1/001 ,  H03M1/08 ,  H03M1/0845 ,  H03M1/66 ,  H03M1/665 ,  H03M1/742

Abstract: According to an embodiment, a power supply noise cancelling circuit includes a generator, a first multiplier, a subtractor and a digital-to-analog converter. The generator generates a sine wave signal. The first multiplier multiplies a digital input signal by a digital signal based on the sine wave signal to generate a first digital product signal. The subtractor subtracts a digital signal based on the first digital product signal from the digital input signal to generate a digital difference signal. The digital-to-analog converter performs a digital-to-analog conversion on the digital difference signal to obtain an analog output signal.

Abstract translation: 根据实施例，电源噪声消除电路包括发生器，第一乘法器，减法器和数模转换器。 发生器产生正弦波信号。 第一乘法器基于正弦波信号将数字输入信号乘以数字信号以产生第一数字乘积信号。 减法器基于来自数字输入信号的第一数字乘积信号减去数字信号，以产生数字差分信号。 数模转换器对数字差分信号执行数模转换以获得模拟输出信号。

公开(公告)号：US20150256191A1

公开(公告)日：2015-09-10

申请号：US14437237

申请日：2014-08-13

Applicant: ASAHI KASEI MICRODEVICES CORPORATION

Inventor： Ryuzo Yamamoto ,  Junya Nakanishi ,  Seiko Nakamoto

IPC: H03M1/06 ,  H03M1/12 ,  H03M1/66 ,  H03M1/08

CPC classification number: H03M1/0614 ,  H03F1/3247 ,  H03M1/00 ,  H03M1/08 ,  H03M1/0863 ,  H03M1/12 ,  H03M1/66 ,  H03M1/747 ,  H04B2001/7154 ,  H04L27/2647

Abstract: The present invention relates to a control method of a D/A converter, a D/A converter, a control method of an A/D converter, and an A/D converter that can suppress an existing n-th harmonic without using a large-scale circuit, such as a bootstrap. A D/A converter (10) of the present invention is a D/A converter (10) that can suppress the generation of an existing n-th harmonic (n is an integer of 2 or more) of an analog output signal. The D/A converter (10) includes a D/A conversion unit (11) that converts an input digital signal into an analog signal and a control unit (12) that arbitrarily controls the timing of the sampling phase and the integral phase of the D/A conversion unit (11). The D/A conversion unit (11) is configured to generate an arbitrary n-th harmonic and superimpose the arbitrary n-th harmonic on an analog output signal including the existing n-th harmonic.

Abstract translation: 本发明涉及D / A转换器的控制方法，D / A转换器，A / D转换器的控制方法和可以抑制现有的n次谐波而不使用大的A / D转换器 尺度电路，例如自举。 本发明的D / A转换器（10）是可以抑制模拟输出信号的现有n次谐波（n为2以上的整数）的产生的D / A转换器（10）。 D / A转换器（10）包括将输入数字信号转换为模拟信号的D / A转换单元（11）和任意控制采样相位的定时和 D / A转换单元（11）。 D / A转换单元（11）被配置为产生任意的n次谐波，并且将任意的n次谐波叠加在包括现有的n次谐波的模拟输出信号上。

公开(公告)号：US20140361915A1

公开(公告)日：2014-12-11

申请号：US14294300

申请日：2014-06-03

Applicant: STMicroelectronics SA ,  STMicroelectronics International N.V.

Inventor： Stéphane LE TUAL ,  Pratap Narayan SINGH

IPC: H03M1/08 ,  H03K3/013

CPC classification number: H03M1/08 ,  G11C27/024 ,  G11C27/026 ,  H03K3/013 ,  H03K19/018528

Abstract: The invention concerns a circuit comprising: a first transistor (202) having a first main current node coupled to a first voltage signal (CNVDD), a control node coupled to a second voltage signal (CPVDD) and a second main current node coupled to an output node (206) of the circuit; a second transistor (204) having a first main current node coupled to a third voltage signal (CPGND), a control node coupled to a fourth voltage signal (CPGND) and a second main current node coupled to said output node of the circuit; and circuitry (210, 212) adapted to generate said first, second, third and fourth voltage signals based on a pair of differential input signals (CP, CN), wherein said first and second voltage signals are both referenced to a first supply voltage (VDD) and wherein said third and fourth voltage signals are both referenced to a second supply voltage (GND).

Abstract translation: 本发明涉及一种电路，包括：具有耦合到第一电压信号（CNVDD）的第一主电流节点的第一晶体管（202），耦合到第二电压信号（CPVDD）的控制节点和耦合到第一电流信号 输出节点（206）; 第二晶体管（204），其具有耦合到第三电压信号（CPGND）的第一主电流节点，耦合到第四电压信号（CPGND）的控制节点和耦合到所述电路的所述输出节点的第二主电流节点; 以及适于基于一对差分输入信号（CP，CN）产生所述第一，第二，第三和第四电压信号的电路（210,212），其中所述第一和第二电压信号都参考第一电源电压 VDD），并且其中所述第三和第四电压信号都参考第二电源电压（GND）。

公开(公告)号：US08902094B1

公开(公告)日：2014-12-02

申请号：US14087457

申请日：2013-11-22

Applicant: Broadcom Corporation

Inventor： Heng Zhang ,  Delong Cui ,  Jun Cao

IPC: H03M1/00 ,  H03M1/08 ,  H03M1/50 ,  H03M1/12 ,  H03L7/081 ,  H04L7/00 ,  H03K5/135 ,  H03L7/089

CPC classification number: H03M1/08 ,  H03K5/135 ,  H03L7/0812 ,  H03L7/0814 ,  H03L7/0891 ,  H03M1/00 ,  H03M1/12 ,  H03M1/1215 ,  H04L7/0008

Abstract: A first clock generator receives an input clock, generates a first clock signal for use in a first level of a multilevel track and hold circuit of a time-interleaved analog to digital convertor, and generates a time-leading version of the first clock signal. A plurality of second clock generators receive the input clock and generate a corresponding plurality of second clock signals for use in a second level of the multi-level track and hold circuit. The plurality of second level clock generators include an adjustable delay that delays a corresponding one of the plurality of second clock signals by a delay amount that is determined based on a delay control signal. A feedback controller generates the delay control signal based on the time-leading version of the first clock signal and further based on the corresponding one of the plurality of second clock signals.

Abstract translation: 第一时钟发生器接收输入时钟，产生用于时间交织的模数转换器的多电平跟踪和保持电路的第一电平的第一时钟信号，并产生第一时钟信号的时间领先的版本。 多个第二时钟发生器接收输入时钟并产生对应的多个第二时钟信号，以在多电平跟踪和保持电路的第二电平中使用。 多个第二电平时钟发生器包括可调节的延迟，其延迟多个第二时钟信号中的相应一个第二时钟信号的延迟量，该延迟量基于延迟控制信号确定。 反馈控制器基于第一时钟信号的时间引导版本并且还基于多个第二时钟信号中的相应一个产生延迟控制信号。

公开(公告)号：US20140285370A1

公开(公告)日：2014-09-25

申请号：US14300657

申请日：2014-06-10

Applicant: PANASONIC CORPORATION

Inventor： Takuji MIKI ,  Kazuo MATSUKAWA ,  Takashi MORIE ,  Shiro SAKIYAMA

IPC: H03M1/08 ,  H03M1/46

CPC classification number: H03M1/08 ,  H03M1/00 ,  H03M1/0641 ,  H03M1/12 ,  H03M1/466 ,  H03M1/468 ,  H03M1/804 ,  H03M3/30

Abstract: In a successive approximation AD converter, a noise generator outputs the output of a ΔΣ modulator as a noise signal. A selector circuit can output the noise signal, in place of a digital signal for generating a comparison-target voltage for the next bit, to a capacitor element of a capacitance DAC. During sampling of an analog input voltage, the noise signal is supplied to the capacitance DAC via the selector circuit, and thereafter normal successive approximation operation is executed.

Abstract translation: 在逐次逼近AD转换器中，噪声发生器输出＆Dgr＆amp; 调制器作为噪声信号。 选择器电路可以代替用于产生下一位的比较目标电压的数字信号，将噪声信号输出到电容DAC的电容器元件。 在采样模拟输入电压时，噪声信号通过选择电路提供给电容DAC，之后执行正常的逐次逼近操作。

公开(公告)号：US20140252207A1

公开(公告)日：2014-09-11

申请号：US14193370

申请日：2014-02-28

Applicant: Kabushiki Kaisha Toshiba

Inventor： Ryuta OKAMOTO

IPC: H03M1/12 ,  H04N5/357

CPC classification number: H04N5/357 ,  H03M1/00 ,  H03M1/08 ,  H03M1/12 ,  H03M1/403 ,  H04N5/378

Abstract: An ADC includes a comparator and first and second amplifier circuits including a fully-differential operational amplifier. The comparator converts an analog signal output from the operational amplifier into digital data. The first amplifier circuit stores charge corresponding to a signal having a phase reverse to an input signal in each of a pair of capacitors during a first period and transfers the charge in one of the pair of capacitors to the other via the operational amplifier during a second period to amplify the reversed phase signal twofold. The second amplifier circuit amplifies the input signal twofold similarly to the first amplifier circuit.

Abstract translation: ADC包括比较器和包括全差分运算放大器的第一和第二放大器电路。 比较器将从运算放大器输出的模拟信号转换为数字数据。 第一放大器电路在第一时段期间存储对应于与一对电容器中的每一个中的输入信号相反的信号的电荷的电荷，并且在第二时间段期间经由运算放大器将该一对电容器中的电荷传送到另一个电容器 周期将反相信号放大两倍。 第二放大器电路类似于第一放大器电路将输入信号放大两倍。

公开(公告)号：US20140218222A1

公开(公告)日：2014-08-07

申请号：US14153251

申请日：2014-01-13

Applicant: IMAGINATION TECHNOLOGIES, LTD.

Inventor： Taku YAMAGATA ,  Adrian John ANDERSON

IPC: H03M1/08 ,  H03M1/12

CPC classification number: H03M1/08 ,  H03G3/3052 ,  H03M1/12 ,  H03M1/185

Abstract: Methods and circuits for controlling an automatic gain control (AGC) circuit wherein the AGC circuit is used to adjust the gain of a signal input to an analog to digital converter. The method includes obtaining a plurality of samples from the output of the analog to digital converter and determining whether the amplitude of each sample is greater than a threshold amplitude value. If the amplitude of a sample is greater than the threshold amplitude value then a counter value is incremented. The target average amplitude of the automatic gain control circuit is then periodically adjusted based on the counter value.

Abstract translation: 用于控制自动增益控制（AGC）电路的方法和电路，其中AGC电路用于调节输入到模数转换器的信号的增益。 该方法包括从模数转换器的输出获得多个样本，并确定每个样本的幅度是否大于阈值振幅值。 如果样本的幅度大于阈值振幅值，则计数器值增加。 然后基于计数器值周期性地调整自动增益控制电路的目标平均幅度。

公开(公告)号：US20140210653A1

公开(公告)日：2014-07-31

申请号：US14163560

申请日：2014-01-24

Applicant: Technische Universiteit Eindhoven

Inventor： Pieter Joost Adriaan Harpe

IPC: H03M1/12

CPC classification number: H03M1/0697 ,  H03M1/02 ,  H03M1/08 ,  H03M1/12 ,  H03M1/38 ,  H03M1/462

Abstract: A successive operation register (SAR) analog-to-digital converter (ADC) circuit includes a bit reliability circuit that detects a delay time of the voltage comparator and, if the detected delay time is greater than a delay threshold time τMV, outputs a bit reliability decision signal; a digital noise reduction circuit that is selectively activated if the bit reliability decision signal indicates the detected delay time is greater than the delay threshold time τMV and produces a noise-reduced decision output that supersedes the decision output of the voltage comparator. In a preferred embodiment, the digital noise reduction circuit uses a multiple voting logic to produce a majority vote value as the noise-reduced decision output.

Abstract translation: 连续运算寄存器（SAR）模数转换器（ADC）电路包括检测电压比较器的延迟时间的位可靠性电路，并且如果检测到的延迟时间大于延迟阈值时间τMV，则输出一位 可靠性决策信号; 如果位可靠性判定信号指示检测到的延迟时间，则选择性地激活数字噪声降低电路，并产生取代电压比较器的判定输出的噪声降低判定输出。 在优选实施例中，数字降噪电路使用多个投票逻辑来产生多数投票值作为噪声降低的决策输出。

公开(公告)号：US08773307B2

公开(公告)日：2014-07-08

申请号：US12952029

申请日：2010-11-22

Applicant: Donald C. D. Chang ,  Yulan Sun ,  Yuanchang Liu

Inventor： Donald C. D. Chang ,  Yulan Sun ,  Yuanchang Liu

IPC: G01S3/16 ,  H01Q3/00

CPC classification number: H03M1/002 ,  H03M1/0641 ,  H03M1/08 ,  H03M1/12 ,  H03M1/1205 ,  H03M1/1215 ,  H03M1/188 ,  H03M1/20 ,  H04B1/0475 ,  H04B1/123 ,  H04B7/10 ,  H04L27/06

Abstract: A novel wide null forming system achieves both wide bandwidth and beam width null through employing an antenna array to receive and transmit signals to which a complex null weight vector, calculated by perturbation program, is applied. The novel wide null forming system includes a multiple-element antenna array for receiving or transmitting signals. Multiple conditioning units matching the number of elements is present to condition the signals for proper reception and analysis, after which a series of complex multiplier processors adds complex weights. After being weighted each constituent beam is combined in an adding processor to form one composite beam for use by the user.

Abstract translation: 通过采用天线阵列来接收和发送通过扰动程序计算的复零零权重向量的信号，新的宽零空位形成系统实现宽带宽和波束宽度零。 新的宽零位成形系统包括用于接收或发送信号的多元件天线阵列。 存在与元件数量相匹配的多个调节单元来调节信号以进行适当的接收和分析，之后一系列复杂乘法器处理器增加了复杂的权重。 在加权之后，每个组成光束在加法处理器中组合以形成用户使用的一个组合光束。

公开(公告)号：US20140118173A1

公开(公告)日：2014-05-01

申请号：US13784842

申请日：2013-03-05

Applicant: NOVATEK MICROELECTRONICS CORP.

Inventor： Po-Chin Hu ,  LIMING XIU

IPC: H03M1/12

CPC classification number: H03M1/12 ,  H03M1/00 ,  H03M1/08 ,  H03M1/1245 ,  H04L25/067 ,  H04L27/2647

Abstract: A method of reducing a water-wave noise for an analog to digital conversion includes performing sampling on an analog input signal; determining whether the analog input signal is interfered with by a periodic noise such that a water wave is generated; and executing one or both of the following steps when the analog input signal is interfered with by the periodic noise: adjusting a sampling frequency of the ADC, and adjusting a noise frequency of the periodic noise.

Abstract translation: 降低模数转换的水波噪声的方法包括对模拟输入信号进行采样; 确定模拟输入信号是否被产生水波的周期性噪声干扰; 并且当模拟输入信号被周期性噪声干扰时执行以下步骤中的一个或两个：调整ADC的采样频率以及调整周期性噪声的噪声频率。