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公开(公告)号：US20240259028A1
公开(公告)日：2024-08-01
申请号：US18102504
申请日：2023-01-27
Applicant: Analog Devices, Inc.
Inventor： Enrique ALVAREZ FONTECILLA , Paul WILKINS
IPC: H03M1/08
CPC classification number: H03M1/08
Abstract: Aspects of the present disclosure include receiving a digital input signal having an identified value, determining a number of a plurality of converters, determining, based on the identified value and the number, a minimum number of one or more minimum output configurations, parsing the digital input into a plurality of individual bits, and transmitting the plurality of individual bits to the plurality of converters based on an output configuration of the one or more minimum output configurations.
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公开(公告)号：US20240154619A1
公开(公告)日：2024-05-09
申请号：US18279498
申请日：2022-02-21
Applicant: ams Sensors Germany GmbH
Inventor： Massimo MASCOTTO , Dalibor STOJKOVIC , Steffen FRITZLAR
Abstract: A signal processing circuit includes a first current sensor input, a second current sensor input, a voltage sensor input for receiving a sensor voltage, a first selection unit, a second selection unit, a current analog-digital converter (ADC), a voltage ADC, digital processing block, and a current-voltage converter. The first selection unit includes a first current input coupled to the first current sensor input, and a second current input coupled to the second current sensor input. The second selection unit includes a first voltage input coupled to the voltage sensor input and a second voltage input. The current ADC is coupled to a first current output. The voltage ADC is coupled to a voltage output. The digital processing block is coupled to outputs of the current ADC and the voltage ADC. The current-voltage converter is coupled between a second current output and the second voltage input.
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公开(公告)号：US11653112B2
公开(公告)日：2023-05-16
申请号：US17101628
申请日：2020-11-23
Applicant: Raytheon Company
Inventor： Christian M. Boemler
Abstract: A method including collecting analog image data from an imaging array wherein the analog image data includes analog image data from a plurality of imaging pixels and from a plurality of opaque pixels. Each row of the imaging array includes both imaging pixels and opaque pixels. Opaque subtraction is performed in an analog domain, wherein biases determined in the opaque pixels for a given row of the imaging array are subtracted from the analog image data of the imaging pixels of that given row for each row of the imaging array. Performing opaque subtraction includes suppressing outliers in the analog image data from the plurality of opaque pixels. The method includes performing analog to digital conversion (ADC) on the analog image data to produce digital image data for the imaging pixels. ADC is performed after opaque subtraction in the analog domain.
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公开(公告)号：US20190158771A1
公开(公告)日：2019-05-23
申请号：US16253365
申请日：2019-01-22
Applicant: SONY CORPORATION
Inventor： Masaaki BAIRO
IPC: H04N5/378 , H01L23/522 , H04N9/04 , H03M1/08 , H01L21/822 , H03M1/56 , H01L27/04
CPC classification number: H04N5/378 , H01L21/822 , H01L23/5223 , H01L27/04 , H03M1/08 , H03M1/123 , H03M1/56 , H04N9/045
Abstract: An analog-to-digital converter includes a comparator having paired differential input ends, and a first capacitor and a second capacitor each provided at respective differential input ends. The first capacitor includes a plurality of first sub-capacitors that are coupled side by side with one another, and the second capacitor includes a plurality of second sub-capacitors that are coupled side by side with one another. The plurality of first sub-capacitors and the plurality of second sub-capacitors are mixedly arranged in each column of a plurality of columns.
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公开(公告)号：US20190074843A1
公开(公告)日：2019-03-07
申请号：US16179405
申请日：2018-11-02
Applicant: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
Inventor： YA-NAN WEN , YINGSI LIANG
CPC classification number: H03M1/08 , H03M3/424 , H03M3/45 , H03M3/452 , H03M3/454 , H03M3/456 , H03M3/46 , H03M3/462 , H03M7/3026
Abstract: The present disclosure provides a converting module formed in a first die. The first die is coupled to a bus having a bus bit width. The converting module includes an analog-to-digital converter, configured to generate a first digital signal having a first bit width different from the bus bit width; and a sigma-delta modulator, coupled to the analog-to-digital converter, and configured to generate a second digital signal according to the first digital signal. The second digital signal has a bit width equal to the bus bit width. The sigma-delta modulator includes a filter and a quantizer. The number of bits outputted by the quantizer is equal to the bus bit width.
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Patent Agency Ranking
公开(公告)号：US20180278874A1
公开(公告)日：2018-09-27
申请号：US15989543
申请日：2018-05-25
Applicant: SONY CORPORATION
Inventor： YOSHIAKI INADA
IPC: H04N5/378 , H04N5/3745 , H04N5/374
CPC classification number: H04N5/378 , H03M1/08 , H03M1/123 , H03M1/203 , H03M1/56 , H04N5/363 , H04N5/3698 , H04N5/374 , H04N5/37455
Abstract: The present technology relates to an image sensor, an electronic apparatus, a comparator, and a drive method enabling achievement of a noise reduction while maintaining high speed of AD conversion. An ADC for performing AD conversion for an electrical signal output from a pixel includes a comparator that compares the electrical signal and a reference signal, a level of which is changed and a counter that counts time necessary for a change of the reference signal to a coincidence of the electrical signal and the reference signal on the basis of output signals from the comparator. The comparator includes a differential amplifier that outputs a comparison result signal indicating a comparison result obtained by comparing the electrical signal and the reference signal and a plurality of output amplifiers that outputs signals obtained by amplifying the comparison result signal output from the differential amplifier as the output signals at different timings.
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公开(公告)号：US20180212614A1
公开(公告)日：2018-07-26
申请号：US15927157
申请日：2018-03-21
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Jagannathan VENKATARAMAN , Eeshan MIGLANI
CPC classification number: H03M1/08 , H03K17/162 , H03K17/165 , H03M1/742
Abstract: At least some embodiments are directed to a system that comprises a differential switch network comprising first and second output nodes, first and second transistors coupled to the network, and first and second resistors coupled to the first and second transistors. The DAC also comprises a voltage source coupled to the first resistor and a ground connection coupled to the second resistor. The DAC further includes a capacitor coupled to the first and second transistors and to the second resistor.
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公开(公告)号：US09954549B2
公开(公告)日：2018-04-24
申请号：US15595045
申请日：2017-05-15
Applicant: Marvell World Trade Ltd.
Inventor： Alessandro Venca , Claudio Nani , Nicola Ghittori , Alessandro Bosi
IPC: H03M1/66 , H03M1/80 , H03M1/68 , H03M1/08 , H03M1/10 , H03M1/12 , H03M1/38 , H03M1/46 , H03M3/00
CPC classification number: H03M1/667 , H03M1/08 , H03M1/1009 , H03M1/1245 , H03M1/38 , H03M1/462 , H03M1/466 , H03M1/68 , H03M1/80 , H03M1/804 , H03M3/322
Abstract: A hybrid digital-to-analog converter including a charge-sharing digital-to-analog converter and a charge redistribution digital-to-analog converter is provided. The charge-sharing digital-to-analog converter is configured to receive a digital input signal having multiple bits. The bits include a most-significant-bit and a least-significant-bit. The charge-sharing digital-to-analog converter is configured to convert the most-significant-bit to provide a first portion of an analog signal and selectively share charges of first capacitors during a successive approximation of the most-significant-bit. The charge redistribution digital-to-analog converter is configured to convert the least-significant-bit to provide a second portion of the analog signal. The charge redistribution digital-to-analog converter performs charge redistribution by selectively connecting second capacitors to receive reference voltages during a successive approximation of the least-significant-bit.
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公开(公告)号：US09893738B2
公开(公告)日：2018-02-13
申请号：US15469712
申请日：2017-03-27
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jae-hoon Lee , Seung-hyun Oh , Jong-woo Lee
CPC classification number: H03M1/1245 , G11C27/02 , G11C27/024 , H03M1/08 , H03M1/468
Abstract: An analog-to-digital converter includes a sample hold circuit configured to receive an analog input signal based on an operating mode, the operating mode being one of at least two modes including a sample mode and a hold mode. The sample hold circuit includes a first transistor including a control terminal and a first terminal, the first transistor configured to receive a control signal via the control terminal and receive the analog input signal via the first terminal. The analog-to-digital converter further includes a bootstrap switch operationally connected to the control terminal and the first terminal of the first transistor, the bootstrap switch configured to form a first current path from a power source based on the analog input signal and a boosted voltage of the control terminal of the first transistor in the sample mode, the control terminal bing along the first current path in the sample mode.
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公开(公告)号：US20170359077A1
公开(公告)日：2017-12-14
申请号：US15618620
申请日：2017-06-09
Applicant: Analog Devices Global
Inventor： Dennis A. DEMPSEY , Harvey T. MERCADO
IPC: H03M1/08
Abstract: A buffer is provided where a part of the buffer is implemented in switched capacitor or other analog discrete time processing circuitry and a dynamic response characteristic, such as an effective gain or charge transfer coefficient between the input stage and an output stage is digitally controllable. This means that the buffer can be driven as if it was a system controlled by, for example a three (3) term controller, giving rise to greater, digital flexibility in tailoring the buffer's transient response.
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