公开(公告)号：US20180188652A1

公开(公告)日：2018-07-05

申请号：US15905969

申请日：2018-02-27

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Jiale SU

IPC: G03F7/20 ,  G03F1/38

CPC classification number: G03F7/2035 ,  G03F1/38 ,  G03F7/203

Abstract: A photolithography system based on a high step slope may include a depositing unit configured to manufacture a sacrificial layer having high step slope on a substrate. The system may also include a coating unit configured to coat a photoresist layer on the sacrificial layer by performing a spin-on PR coating process to form a photolithographic layer. The system may further include a photolithography unit configured to perform one or more photolithography processes to the photolithographic layer. The photolithography unit may comprise a plurality of masks of compensation patterns. The compensation pattern may comprise a slope-top compensation pattern and a slope compensation pattern.

公开(公告)号：US09954074B2

公开(公告)日：2018-04-24

申请号：US14902517

申请日：2014-07-22

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Shengrong Zhong ,  Xiaoshe Deng ,  Genyi Wang ,  Dongfei Zhou

IPC: H01L29/66 ,  H01L29/40 ,  H01L29/739 ,  H01L29/06 ,  H01L29/10 ,  H01L21/02 ,  H01L21/265

CPC classification number: H01L29/66333 ,  H01L21/02233 ,  H01L21/26513 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/7395

Abstract: An insulated gate bipolar transistor and a manufacturing method therefor. The insulated gate bipolar transistor comprises a semiconductor substrate (1) of a first conductive type, which is provided with a first major surface (1S1) and a second major surface (1S2), wherein the semiconductor substrate (1) comprises a primitive cell area (2) and a terminal protection area (4) which is located outside the primitive cell area; a first semiconductor layer (5) of a first conductive type which is formed at the side of the first major surface of the semiconductor substrate (1), wherein the doping concentration of the first semiconductor layer (5) is higher than the doping concentration of the semiconductor substrate (1); and an insulated gate transistor unit which is formed at the side of the first major surface of the first semiconductor layer (5) in the primitive cell area, wherein the insulated gate transistor unit is conducted, a channel of a first conductive type is formed. Compared with the prior art, the present invention not only can improve the voltage resistance reliability of the insulted gate bipolar transistor, but also can reduce the forward conductive voltage drop of the insulated gate bipolar transistor.

公开(公告)号：US09952609B2

公开(公告)日：2018-04-24

申请号：US15327916

申请日：2015-08-18

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Nan Zhang ,  Jing Zhou

IPC: G05F1/56 ,  G05F1/575 ,  G05F1/46

CPC classification number: G05F1/468 ,  G05F1/56 ,  G05F1/575

Abstract: A low dropout linear regulator circuit comprises a voltage reference source module (100), an error amplifier (200), a reference voltage determining module (300), a power transmission device (400) and a feedback module (500); wherein the voltage reference source module (100) provides a reference voltage for the error amplifier (200), the reference voltage determining module (300) controls an enablement of the error amplifier (200) according to whether the voltage reference source module (100) is completely started, the error amplifier (200) controls ON/OFF of the power transmission device (400) according to the reference voltage provided by the voltage reference source module (100) and a feedback voltage provided by the feedback module (500). A chip having the above low dropout linear regulator circuit and a electronic device having the above chip are provided.

公开(公告)号：US09947785B2

公开(公告)日：2018-04-17

申请号：US15318857

申请日：2015-06-30

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Guangtao Han ,  Guipeng Sun

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/40 ,  H01L29/47 ,  H01L29/10 ,  H01L29/49 ,  H01L29/423 ,  H01L29/06 ,  H01L29/808

CPC classification number: H01L29/7831 ,  H01L29/0607 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1066 ,  H01L29/1083 ,  H01L29/408 ,  H01L29/4238 ,  H01L29/47 ,  H01L29/4916 ,  H01L29/66484 ,  H01L29/66681 ,  H01L29/66901 ,  H01L29/782 ,  H01L29/808

Abstract: The present invention relates to a junction field effect transistor. The junction field effect transistor comprises a substrate (10), a buried layer in the substrate, a first well region (32) and a second well region (34) that are on the buried layer, a source lead-out region (50), a drain lead-out region (60), and a first gate lead-out region (42) that are in the first well region (32), and a second gate lead-out region (44) in the second well region (34). A Schottky junction interface (70) is disposed on the surface of the first well region (32). The Schottky junction interface (70) is located between the first gate lead-out region (42) and the drain lead-out region (60), and is isolated from the first gate lead-out region (42) and the drain lead-out region (60) by means of isolation structures. The present invention also relates to a manufacturing method for a junction field effect transistor.

公开(公告)号：US20180102406A1

公开(公告)日：2018-04-12

申请号：US15840791

申请日：2017-12-13

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Shengrong ZHONG ,  Dongfei ZHOU ,  Xiaoshe DENG ,  Genyi WANG

IPC: H01L29/06 ,  H01L29/16 ,  H01L21/761 ,  H01L29/04 ,  H01L29/161 ,  H01L29/66 ,  H01L29/10 ,  H01L29/739 ,  H01L29/20

CPC classification number: H01L29/0623 ,  H01L21/761 ,  H01L29/045 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/20 ,  H01L29/66333 ,  H01L29/6634 ,  H01L29/7395 ,  H01L29/7396

Abstract: An insulated gate bipolar transistor (100) is provided. A substrate (10) of the insulated gate bipolar transistor (100) is of an N type. A P-type region (16) is disposed on a back of the N-type substrate. A back metal structure (18) is disposed on a back of the P-type region (16). A terminal protection ring is disposed in a terminal structure. A polysilicon gate (31) is disposed on a front surface of the substrate (10) in an active region. Sidewalls (72) are disposed at two sides of the polysilicon gate (31) on the substrate (10). An interlayer medium (81) covered with the polysilicon gate (31) and the sidewalls (72) is disposed on the substrate (10). The interlayer medium (81) is covered with a metal lead wire layer (91). An N-type carrier enhancement region (41) is disposed in the substrate (10) in the active region. A P-type body region (51) is disposed in the carrier enhancement region (41). An N-type heavily doped region (61) is disposed in the P-type body region (51). A P-type heavily doped region (71) is disposed in the N-type heavily doped region (61). An inward recessed shallow pit (62) with a depth of 0.15 to 0.3 micrometers is formed on a surface of the P-type heavily doped region (71). By disposing the carrier enhancement region (41), the carrier concentration of a channel can be increased and a forward voltage drop can be reduced; in addition, the shallow pit (62) can make a device obtain good impurity distribution and a large metal contact area, thereby improving the performance of the device.

公开(公告)号：US20180069107A1

公开(公告)日：2018-03-08

申请号：US15537753

申请日：2015-09-28

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Shukun QI

IPC: H01L29/739 ,  H01L29/423 ,  H01L21/265 ,  H01L21/324 ,  H01L21/225 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/762 ,  H01L29/66

CPC classification number: H01L29/7394 ,  H01L21/02236 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/7624 ,  H01L29/0623 ,  H01L29/0834 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/66325

Abstract: Provided is a lateral insulated-gate bipolar transistor (LIGBT), comprising a substrate (10), an anode terminal and a cathode terminal on the substrate (10), and a drift region (30) and a gate (61) located between the anode terminal and the cathode terminal. The anode terminal comprises a P-type buried layer (52) on the substrate (10), an N-type buffer region (54) on the P-type buried layer (52), and a P+ collector region (56) on the surface of the N-type buffer region (54). The LIGBT further comprises a trench gate adjacent to the anode terminal, wherein the trench gate penetrates from the surfaces of the N-type buffer region (54) and the P+ collector region (56) to the P-type buried layer (52), and the trench gate comprises an oxidation layer (51) on the inner surface of a trench and polysilicon (53) filled into the oxidation layer.

公开(公告)号：US09902613B2

公开(公告)日：2018-02-27

申请号：US15315640

申请日：2015-08-19

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Errong Jing

IPC: H01L21/00 ,  B81C3/00

CPC classification number: B81C3/004 ,  B81C1/00 ,  B81C1/00603 ,  B81C3/00 ,  B81C2203/051 ,  G03F9/00 ,  H01L21/68

Abstract: A positioning method in a microprocessing process of bulk silicon comprises the steps of: fabricating, on a first surface of a first substrate (10), a first pattern (100), a stepper photo-etching machine alignment mark (200) for positioning the first pattern, and a double-sided photo-etching machine first alignment mark (300) for positioning the stepper photo-etching machine alignment mark; fabricating, on a second surface, opposite to the first surface, of the first substrate, a double-sided photo-etching machine second alignment mark (400) corresponding to the double-sided photo-etching machine first alignment mark; bonding a second substrate (20) on the first surface of the first substrate; performing thinning on a first surface of the second substrate; fabricating, on the first surface of the second substrate, a double-sided photo-etching machine third alignment mark (500) corresponding to the double-sided photo-etching machine second alignment mark; and finding, on the first surface of the second substrate by using the double-sided photo-etching machine third alignment mark, a corresponding position of the stepper photo-etching machine alignment mark.

公开(公告)号：US20170186856A1

公开(公告)日：2017-06-29

申请号：US15313233

申请日：2015-08-18

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Guangtao HAN

IPC: H01L29/66 ,  H01L21/266 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/78 ,  H01L21/265 ,  H01L21/28

CPC classification number: H01L29/66681 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/28035 ,  H01L21/28114 ,  H01L21/28123 ,  H01L29/1037 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/7816

Abstract: A method for manufacturing an LDMOS device includes: providing a semiconductor substrate (200), forming a drift region (201) in the semiconductor substrate (200), forming a gate material layer on the semiconductor substrate (200), and forming a negative photoresist layer (204) on the gate material layer; patterning the negative photoresist layer (204), and etching the gate material layer by using the patterned negative photoresist layer (204) as a mask so as to form a gate (203); forming a photoresist layer having an opening on the semiconductor substrate (200) and the patterned negative photoresist layer (204), the opening corresponding to a predetermined position for forming a body region (206); and injecting the body region (206) by using the gate (203) and the negative photoresist layer (204) located above the gate (203) as a self-alignment layer, so as to form a channel region.

公开(公告)号：US09666682B2

公开(公告)日：2017-05-30

申请号：US14902302

申请日：2014-09-02

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Wanli Wang ,  Xiaoshe Deng ,  Genyi Wang ,  Qiang Rui

IPC: H01L29/66 ,  H01L29/739 ,  H01L29/06 ,  H01L21/268 ,  H01L21/324 ,  H01L29/417 ,  H01L29/08 ,  H01L21/265 ,  H01L21/308

CPC classification number: H01L29/66333 ,  H01L21/26513 ,  H01L21/268 ,  H01L21/308 ,  H01L21/3247 ,  H01L29/0657 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/41716 ,  H01L29/7395

Abstract: A reverse conducting insulated gate bipolar transistor (IGBT) manufacturing method, comprising the following steps: providing a substrate having an IGBT structure formed on the front surface thereof; implanting P+ ions onto the back surface of the substrate; forming a channel on the back surface of the substrate through photolithography and etching processes; planarizing the back surface of the substrate through a laser scanning process to form P-type and N-type interval structures; and forming a back surface collector by conducting a back metalizing process on the back surface of the substrate. Laser scanning process can process only the back surface structure requiring annealing, thus solve the problem of the front surface structure of the reverse conducting IGBT restricting back surface annealing to a low temperature, improving the P-type and N-type impurity activation efficiency in the back surface structure of the reverse conducting IGBT, and enhancing the performance of the reverse conducting IGBT.

公开(公告)号：US20170133505A1

公开(公告)日：2017-05-11

申请号：US15318857

申请日：2015-06-30

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Guangtao HAN ,  Guipeng SUN

IPC: H01L29/78 ,  H01L29/47 ,  H01L29/66 ,  H01L29/49 ,  H01L29/423 ,  H01L29/06 ,  H01L29/40 ,  H01L29/10

CPC classification number: H01L29/7831 ,  H01L29/0607 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1066 ,  H01L29/1083 ,  H01L29/408 ,  H01L29/4238 ,  H01L29/47 ,  H01L29/4916 ,  H01L29/66484 ,  H01L29/66681 ,  H01L29/66901 ,  H01L29/782 ,  H01L29/808

Abstract: The present invention relates to a junction field effect transistor. The junction field effect transistor comprises a substrate (10), a buried layer in the substrate, a first well region (32) and a second well region (34) that are on the buried layer, a source lead-out region (50), a drain lead-out region (60), and a first gate lead-out region (42) that are in the first well region (32), and a second gate lead-out region (44) in the second well region (34). A Schottky junction interface (70) is disposed on the surface of the first well region (32). The Schottky junction interface (70) is located between the first gate lead-out region (42) and the drain lead-out region (60), and is isolated from the first gate lead-out region (42) and the drain lead-out region (60) by means of isolation structures. The present invention also relates to a manufacturing method for a junction field effect transistor.