公开(公告)号：US08372706B2

公开(公告)日：2013-02-12

申请号：US13218720

申请日：2011-08-26

Applicant: Shun-Jang Liao ,  Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang

Inventor： Shun-Jang Liao ,  Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang

IPC: H01L21/8238

CPC classification number: H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7848

Abstract: Provided is a method of fabricating a semiconductor device. A first hard mask layer is formed on a substrate. A second hard mask layer s formed the substrate overlying the first hard mask layer. A dummy gate structure on the substrate is formed on the substrate by using at least one of the first and the second hard mask layers to pattern the dummy gate structure. A spacer element is formed adjacent the dummy gate structure. A strained region on the substrate adjacent the spacer element (e.g., abutting the spacer element). The second hard mask layer and the spacer element are then removed after forming the strained region.

Abstract translation: 提供一种制造半导体器件的方法。 在基板上形成第一硬掩模层。 第二硬掩模层形成覆盖在第一硬掩模层上的基板。 通过使用第一和第二硬掩模层中的至少一个来在衬底上形成伪栅极结构，以对虚拟栅极结构进行图案化。 在虚拟栅极结构附近形成间隔元件。 邻近衬垫元件的衬底上的应变区域（例如，邻接间隔元件）。 然后在形成应变区域之后去除第二硬掩模层和间隔元件。

公开(公告)号：US08361866B2

公开(公告)日：2013-01-29

申请号：US13204461

申请日：2011-08-05

Applicant: Chun-Yi Lee ,  Harry Chuang ,  Ping-Wei Wang ,  Kong-Beng Thei

Inventor： Chun-Yi Lee ,  Harry Chuang ,  Ping-Wei Wang ,  Kong-Beng Thei

IPC: H01L21/8234

CPC classification number: H01L27/0883 ,  G11C11/412 ,  H01L27/092 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848 ,  Y10S438/919

Abstract: A semiconductor structure comprising an SRAM/inverter cell and a method for forming the same are provided, wherein the SRAM/inverter cell has an improved write margin. The SRAM/inverter cell includes a pull-up PMOS device comprising a gate dielectric over the semiconductor substrate, a gate electrode on the gate dielectric wherein the gate electrode comprises a p-type impurity and an n-type impurity, and a stressor formed in a source/drain region. The device drive current of the pull-up PMOS device is reduced due to the counter-doping of the gate electrode.

公开(公告)号：US08304839B2

公开(公告)日：2012-11-06

申请号：US13216114

申请日：2011-08-23

Applicant: Kong-Beng Thei ,  Harry Chuang

Inventor： Kong-Beng Thei ,  Harry Chuang

IPC: H01L27/11

CPC classification number: H01L27/0629 ,  H01L23/5256 ,  H01L28/20 ,  H01L29/66545 ,  H01L29/66628 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: Methods for fabricating a semiconductor device are disclosed. In an example, a method includes forming an isolation region on a substrate, wherein the isolation region extends a depth into the substrate from a substrate surface; forming a recess in the isolation region, wherein the recess is defined by a concave surface of the isolation region; and forming a first gate structure over the substrate surface and a second gate structure over the concave surface of the isolation region.

公开(公告)号：US20120225529A1

公开(公告)日：2012-09-06

申请号：US13465551

申请日：2012-05-07

Applicant: Chieh-Hao Chen ,  Hao-Ming Lien ,  Ssu-Yu Li ,  Jun-Lin Yeh ,  Kang-Cheng Lin ,  Kuo-Tai Huang ,  Chii-Horng Li ,  Chien-Liang Chen ,  Chung-Hau Fei ,  Wen-Chih Yang ,  Jin-Aun Ng ,  Chi Hsin Chang ,  Chun Ming Lin ,  Harry Chuang

Inventor： Chieh-Hao Chen ,  Hao-Ming Lien ,  Ssu-Yu Li ,  Jun-Lin Yeh ,  Kang-Cheng Lin ,  Kuo-Tai Huang ,  Chii-Horng Li ,  Chien-Liang Chen ,  Chung-Hau Fei ,  Wen-Chih Yang ,  Jin-Aun Ng ,  Chi Hsin Chang ,  Chun Ming Lin ,  Harry Chuang

IPC: H01L21/336 ,  H01L21/425

CPC classification number: H01L21/28088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.

Abstract translation: 本公开提供一种半导体器件，其包括半导体衬底和形成在衬底中的晶体管。 晶体管包括具有高k电介质和金属栅极的栅极堆叠，形成在栅极叠层的侧壁上的密封层，密封层具有内边缘和外边缘，内边缘与栅叠层的侧壁相接合 ，形成在密封层的外边缘上的隔离物和形成在栅极堆叠的每一侧上的源极/漏极区域，源极/漏极区域包括与外部电极对准的轻掺杂源极/漏极（LDD）区域 密封层的边缘。

公开(公告)号：US20120196434A1

公开(公告)日：2012-08-02

申请号：US13443550

申请日：2012-04-10

Applicant: Kong-Beng Thei ,  Chung Long Cheng ,  Chung-Shi Liu ,  Harry Chuang ,  Shien-Yang Wu ,  Shi-Bai Chen

Inventor： Kong-Beng Thei ,  Chung Long Cheng ,  Chung-Shi Liu ,  Harry Chuang ,  Shien-Yang Wu ,  Shi-Bai Chen

IPC: H01L21/02

CPC classification number: H01L23/5256 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electrical fuse and a method of forming the same are presented. A first-layer conductive line is formed over a base material. A via is formed over the first-layer conductive line. The via preferably comprises a barrier layer and a conductive material. A second-layer conductive line is formed over the via. A first external pad is formed coupling to the first-layer conductive line. A second external pad is formed coupling to the second-layer conductive line. The via, the first conductive line and the second conductive line are adapted to be an electrical fuse. The electrical fuse can be burned out by applying a current. The vertical structure of the preferred embodiment is suitable to be formed in any layer.

Abstract translation: 提出了电熔丝及其形成方法。 在基材上形成第一层导电线。 在第一层导电线上形成通孔。 通孔优选包括阻挡层和导电材料。 在通孔上形成第二层导电线。 第一外部焊盘形成为耦合到第一层导电线。 第二外部焊盘形成为耦合到第二层导电线。 通孔，第一导线和第二导线适于作为电熔丝。 电熔丝可以通过施加电流而烧坏。 优选实施例的垂直结构适合于形成任何层。

公开(公告)号：US08125051B2

公开(公告)日：2012-02-28

申请号：US12471091

申请日：2009-05-22

Applicant: Harry Chuang ,  Kong-Beng Thei ,  Chiung-Han Yeh ,  Mong-Song Liang ,  Hou-Ju Li ,  Ming-Yuan Wu ,  Tzung-Chi Lee

Inventor： Harry Chuang ,  Kong-Beng Thei ,  Chiung-Han Yeh ,  Mong-Song Liang ,  Hou-Ju Li ,  Ming-Yuan Wu ,  Tzung-Chi Lee

IPC: H01L27/06 ,  H01L21/70 ,  H01L21/338 ,  H01L21/302

CPC classification number: H01L21/8249 ,  H01L27/0623 ,  H01L27/0629 ,  H01L27/0635

Abstract: A semiconductor device is provided that includes a semiconductor substrate having a first region and a second region, transistors having metal gates formed in the first region, an isolation structure formed in the second region, at least one junction device formed proximate the isolation structure in the second region, and a stopping structure formed overlying the isolation structure in the second region.

Abstract translation: 提供一种半导体器件，其包括具有第一区域和第二区域的半导体衬底，在第一区域中形成有金属栅极的晶体管，形成在第二区域中的隔离结构，形成在隔离结构中的至少一个接合器件 第二区域，以及形成在第二区域中的隔离结构上方的停止结构。

公开(公告)号：US20120025329A1

公开(公告)日：2012-02-02

申请号：US13270585

申请日：2011-10-11

Applicant: Ming-Yuah Wu ,  Yi-Shien Mor ,  Chih-Tang Peng ,  Chiung-Han Yeh ,  Kong-Beng Thei ,  Harry Chuang ,  Mong-Song Liang

Inventor： Ming-Yuah Wu ,  Yi-Shien Mor ,  Chih-Tang Peng ,  Chiung-Han Yeh ,  Kong-Beng Thei ,  Harry Chuang ,  Mong-Song Liang

IPC: H01L29/78

CPC classification number: H01L21/823481 ,  H01L21/823468 ,  H01L21/823475 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7833 ,  H01L29/7843

Abstract: A method of forming a semiconductor device includes providing a semiconductor substrate; forming a gate stack on the semiconductor substrate; forming a gate spacer adjacent to a sidewall of the gate stack; thinning the gate spacer; and forming a secondary gate spacer on a sidewall of the gate spacer after the step of thinning the gate spacer.

Abstract translation: 一种形成半导体器件的方法包括提供半导体衬底; 在半导体衬底上形成栅叠层; 形成邻近所述栅叠层的侧壁的栅极间隔; 减薄栅间隔; 以及在所述栅极间隔物变薄的步骤之后，在所述栅极间隔物的侧壁上形成次级栅极间隔物。

公开(公告)号：US08093116B2

公开(公告)日：2012-01-10

申请号：US12364384

申请日：2009-02-02

Applicant: Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang

Inventor： Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang

IPC: H01L21/338

CPC classification number: H01L21/823842 ,  H01L21/28052 ,  H01L21/28088 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: A method is provided that includes providing a substrate, forming a first gate structure in a first region and a second gate structure in a second region, the first and second gate structures each including a high-k dielectric layer, a silicon layer, and a hard mask layer, where the silicon layer of the first gate structure has a different thickness than the silicon layer of the second gate structure, forming an interlayer dielectric (ILD) over the first and second gate structures, performing a chemical mechanical polishing (CMP) on the ILD, removing the silicon layer from the first gate structure thereby forming a first trench, forming a first metal layer to fill in the first trench, removing the hard mask layer and the silicon layer from the second gate structure thereby forming a second trench, and forming a second metal layer to fill in the second trench.

Abstract translation: 提供了一种方法，其包括提供衬底，在第一区域中形成第一栅极结构和在第二区域中形成第二栅极结构，所述第一和第二栅极结构各自包括高k电介质层，硅层和 硬掩模层，其中第一栅极结构的硅层具有与第二栅极结构的硅层不同的厚度，在第一和第二栅极结构上形成层间电介质（ILD），执行化学机械抛光（CMP） 在所述ILD上，从所述第一栅极结构去除所述硅层，从而形成第一沟槽，形成第一金属层以填充所述第一沟槽，从所述第二栅极结构去除所述硬掩模层和所述硅层，由此形成第二沟槽 并且形成第二金属层以填充第二沟槽。

公开(公告)号：US20110303982A1

公开(公告)日：2011-12-15

申请号：US13216034

申请日：2011-08-23

Applicant: Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang

Inventor： Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang

IPC: H01L27/06

CPC classification number: H01L23/5256 ,  H01L21/823878 ,  H01L27/0629 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A semiconductor device is provided which includes a semiconductor substrate, an isolation structure formed in the substrate for isolating an active region of the substrate, the isolation structure being formed of a first material, an active device formed in the active region of the substrate, the active device having a high-k dielectric and metal gate, and a passive device formed in the isolation structure, the passive device being formed of a second material different from the first material and having a predefined resistivity.

Abstract translation: 提供了一种半导体器件，其包括半导体衬底，形成在衬底中用于隔离衬底的有源区的隔离结构，隔离结构由第一材料形成，有源器件形成在衬底的有源区中， 具有高k电介质和金属栅极的有源器件和形成在隔离结构中的无源器件，无源器件由不同于第一材料并具有预定电阻率的第二材料形成。

公开(公告)号：US20110278646A1

公开(公告)日：2011-11-17

申请号：US13194332

申请日：2011-07-29

Applicant: Jin-Aun Ng ,  Wen-Chin Yang ,  Chien-Liang Chen ,  Chung-Hau Fei ,  Maxi Chang ,  Bao-Ru Young ,  Harry Chuang

Inventor： Jin-Aun Ng ,  Wen-Chin Yang ,  Chien-Liang Chen ,  Chung-Hau Fei ,  Maxi Chang ,  Bao-Ru Young ,  Harry Chuang

IPC: H01L27/092

CPC classification number: H01L29/1054 ,  H01L21/823807 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: The present disclosure provides a method including forming STI features in a silicon substrate, defining a first and a second active regions for a PFET and an NFET, respectively; forming a hard mask having an opening to expose the silicon substrate within the first active region; etching the silicon substrate through the opening to form a recess within the first active region; growing a SiGe layer in the recess such that a top surface of the SiGe layer within the first active region and a top surface of the silicon substrate within the second active region are substantially coplanar; forming metal gate material layers; patterning the metal gate material layers to form a metal gate stack on the SiGe layer within the first active region; and forming an eSiGe S/D stressor distributed in both the SiGe layer and the silicon substrate within the first active region.

Abstract translation: 本公开提供了一种方法，包括在硅衬底中形成STI特征，分别为PFET和NFET限定第一和第二有源区; 形成具有开口的硬掩模，以在所述第一有源区域内暴露所述硅衬底; 通过所述开口蚀刻所述硅衬底以在所述第一有源区内形成凹陷; 在凹部中生长SiGe层，使得第一有源区内的SiGe层的顶表面和第二有源区内的硅衬底的顶表面基本上是共面的; 形成金属栅材料层; 图案化金属栅极材料层以在第一有源区内的SiGe层上形成金属栅叠层; 以及在第一有源区内形成分布在SiGe层和硅衬底中的eSiGe S / D应力器。