公开(公告)号：US20120064827A1

公开(公告)日：2012-03-15

申请号：US13229193

申请日：2011-09-09

Applicant: Yong-Hoon KIM ,  Jong-Joo Lee ,  Sang-Youb Lee ,  Young-Don Choi ,  Hee-Seok Lee

Inventor： Yong-Hoon KIM ,  Jong-Joo Lee ,  Sang-Youb Lee ,  Young-Don Choi ,  Hee-Seok Lee

IPC: H04B5/00

CPC classification number: H01L23/645 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/06558 ,  H01L2225/1023 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/3511 ,  H04B5/0012 ,  H04B5/0031 ,  H04B5/0037 ,  H04B5/0075 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device is disclosed including a through electrode. The semiconductor device may include a first semiconductor chip including a transceiver circuit formed on a first surface, a first coupling conductive pattern which is formed on a second surface opposite the first surface, and a through electrode which connects the transceiver circuit and the first coupling conductive pattern. There may be a transceiver located on a second semiconductor chip and including a second coupling conductive pattern facing the first coupling conductive pattern which communicates wirelessly with the first coupling conductive pattern.

Abstract translation: 公开了一种包括通孔的半导体器件。 半导体器件可以包括第一半导体芯片，其包括形成在第一表面上的收发器电路，形成在与第一表面相对的第二表面上的第一耦合导体图案，以及连接收发器电路和第一耦合导电 模式。 可以存在位于第二半导体芯片上的收发器，并且包括面向与第一耦合导电图案无线通信的第一耦合导电图案的第二耦合导电图案。

公开(公告)号：US08061024B2

公开(公告)日：2011-11-22

申请号：US12126364

申请日：2008-05-23

Applicant: Jong-Joo Lee ,  Soon-Yong Hur

Inventor： Jong-Joo Lee ,  Soon-Yong Hur

IPC: H05K3/02

CPC classification number: H05K3/242 ,  H01L21/481 ,  H01L21/4846 ,  H01L23/13 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01327 ,  H01L2924/15311 ,  H05K1/111 ,  H05K3/064 ,  H05K3/243 ,  H05K3/28 ,  H05K2201/10674 ,  H05K2203/0574 ,  H05K2203/175 ,  Y10T29/49126 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: Provided are a circuit board, a semiconductor package including the circuit board, a method of fabricating the circuit board, and a method of fabricating the semiconductor package. The method of fabricating the circuit board includes: forming at least one pair of rows of first bonding pads arranged on a base substrate in a first direction, and a first central plating line formed between the rows of first bonding pads to commonly connect with the rows of first bonding pads; forming an electroplating layer on the first bonding pads; and exposing the base substrate by removing the first central plating line.

Abstract translation: 提供了一种电路板，包括电路板的半导体封装，制造电路板的方法以及制造半导体封装的方法。 制造电路板的方法包括：在第一方向上形成布置在基底基板上的至少一对第一接合焊盘列，以及形成在第一接合焊盘行之间的第一中心电镀线，以与行共同连接 的第一粘接垫; 在所述第一接合焊盘上形成电镀层; 并且通过去除第一中心电镀线来暴露基底。

公开(公告)号：US08039928B2

公开(公告)日：2011-10-18

申请号：US12171035

申请日：2008-07-10

Applicant: Sun-Won Kang ,  Seung-Duk Baek ,  Jong-Joo Lee

Inventor： Sun-Won Kang ,  Seung-Duk Baek ,  Jong-Joo Lee

IPC: H01L23/538

CPC classification number: H01L25/0657 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/15311

Abstract: A chip stack package includes a plurality of chips that are stacked by using adhesive layers as intermediary media, and a through via electrode formed through the chips to electrically couple the chips. The through via electrode is classified as a power supply through via electrode, a ground through via electrode, or a signal transfer through via electrode. The power supply through via electrode and the ground through via electrode are formed of a first material such as copper, and the signal transfer through via electrode is formed of second material such as polycrystalline silicon doped with impurities. The signal transfer through via electrode may have a diametrically smaller cross section than that of each of the power supply through via electrode and the ground through via electrode regardless of their resistivities.

Abstract translation: 芯片堆叠包括通过使用粘合剂层作为中间介质堆叠的多个芯片，以及通过芯片形成的通孔电极以电耦合芯片。 通孔电极通过通孔电极，通过通孔电极的接地或通过通孔电极的信号传输分类为电源。 通过通孔电极和通过通孔电极的接地的电源由诸如铜的第一材料形成，并且通过通孔电极的信号传输由掺杂杂质的多晶硅等第二材料形成。 通过通孔电极的信号传输可以具有比通过通孔电极和通过通孔电极的接地的每个电源的直径更小的横截面，而不管其电阻率如何。

公开(公告)号：US08004081B2

公开(公告)日：2011-08-23

申请号：US12464921

申请日：2009-05-13

Applicant: Jong-joo Lee ,  Seung-duk Baek

Inventor： Jong-joo Lee ,  Seung-duk Baek

IPC: H01L23/04

CPC classification number: H05K1/115 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L25/0657 ,  H01L2223/6616 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/3011 ,  H05K1/0222 ,  H05K1/0251 ,  H05K1/0263 ,  H05K3/429 ,  H05K2201/09636

Abstract: A semiconductor chip package includes a signal interconnection penetrating a semiconductor chip and transmitting a signal to the semiconductor chip and a power interconnection and a ground interconnection penetrating the semiconductor and supplying power and ground to the semiconductor chip. The power interconnection and the ground interconnection are arranged to neighbor each other adjacent to the signal interconnection.

Abstract translation: 半导体芯片封装包括穿透半导体芯片并将信号传输到半导体芯片的信号互连以及穿透半导体的电源互连和接地互连，并向半导体芯片供电和接地。 电源互连和接地互连被布置成邻近信号互连相邻。

公开(公告)号：US20100230811A1

公开(公告)日：2010-09-16

申请号：US12722794

申请日：2010-03-12

Applicant: Dong-Kil Shin ,  Shle-Ge Lee ,  Jong-Joo Lee ,  Jong-Ho Lee

Inventor： Dong-Kil Shin ,  Shle-Ge Lee ,  Jong-Joo Lee ,  Jong-Ho Lee

IPC: H01L23/498

CPC classification number: H01L24/13 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/02126 ,  H01L2224/0401 ,  H01L2224/05558 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/1132 ,  H01L2224/1134 ,  H01L2224/11464 ,  H01L2224/13006 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00012

Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate and a bonding pad disposed thereon. The semiconductor device also includes a passivation layer, a buffer layer, and an insulating layer sequentially stacked on the semiconductor substrate. According to one aspect, a first recess is defined within the passivation layer, the buffer layer, and the insulating layer to expose at least a region of the bonding pad and a second recess is defined within the insulating layer to expose at least a region of the buffer layer and spaced apart from the first recess such that a portion of the insulating layer is interposed therebetween. Further, the semiconductor device includes a conductive solder bump disposed within the first and second recesses. The conductive solder bump may be connected to the bonding pad in the first recess and supported by the buffer layer through a protrusion of the conductive solder bump extending into the second recess.

Abstract translation: 在一个实施例中，半导体器件包括半导体衬底和设置在其上的接合焊盘。 半导体器件还包括依次堆叠在半导体衬底上的钝化层，缓冲层和绝缘层。 根据一个方面，在钝化层，缓冲层和绝缘层内限定第一凹槽，以露出焊盘的至少一个区域，并且在绝缘层内限定第二凹槽，以暴露至少一个区域 缓冲层，并且与第一凹部间隔开，使得绝缘层的一部分插入其间。 此外，半导体器件包括设置在第一和第二凹槽内的导电焊料凸块。 导电焊料凸块可以连接到第一凹槽中的焊盘，并且通过延伸到第二凹部中的导电焊料凸块的突起被缓冲层支撑。

公开(公告)号：US07545037B2

公开(公告)日：2009-06-09

申请号：US11378899

申请日：2006-03-17

Applicant: Jong-Joo Lee

Inventor： Jong-Joo Lee

IPC: H01L23/52

CPC classification number: H01L23/5286 ,  H01L21/84 ,  H01L27/10894 ,  H01L27/1203 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2224/05552

Abstract: Provided are embodiments of semiconductor chips having a redistributed metal interconnection directly connected to power/ground lines of an internal circuit are provided. Embodiments of the semiconductor chips include an internal circuit formed on a semiconductor substrate. A chip pad is disposed on the semiconductor substrate. The chip pad is electrically connected to the internal circuit through an internal interconnection. A passivation layer is provided over the chip pad. A redistributed metal interconnection is provided on the passivation layer. The redistributed metal interconnection directly connects the internal interconnection to the chip pad through a via-hole and a chip pad opening, which penetrate at least the passivation layer. Methods of fabricating the semiconductor chip are also provided.

Abstract translation: 提供了具有直接连接到内部电路的电源/接地线的重分布金属互连的半导体芯片的实施例。 半导体芯片的实施例包括形成在半导体衬底上的内部电路。 芯片焊盘设置在半导体衬底上。 芯片焊盘通过内部互连电连接到内部电路。 钝化层设置在芯片焊盘的上方。 在钝化层上设置重新分布的金属互连。 再分布的金属互连通过穿孔至少钝化层的通孔和芯片焊盘开口将内部互连直接连接到芯片焊盘。 还提供了制造半导体芯片的方法。

公开(公告)号：US20080142248A1

公开(公告)日：2008-06-19

申请号：US11945874

申请日：2007-11-27

Applicant: Jong-Joo LEE

Inventor： Jong-Joo LEE

IPC: H05K1/02

CPC classification number: H05K1/0228 ,  H01L23/13 ,  H01L23/49838 ,  H01L23/50 ,  H01L2224/4824 ,  H01L2924/30107 ,  H05K1/0248 ,  H05K2201/09336 ,  H05K2201/09727 ,  H05K2201/10734 ,  H01L2924/00

Abstract: Provided is a printed circuit board having coplanar LC balance, comprising: an insulation layer, printed circuit patterns formed on the insulation layer, power source wirings supplying power in the printed circuit patterns, and at least three signal wirings formed between the power source wirings, wherein widths of signal wirings far from the power source wirings are wider than widths of signal wirings adjacent to the power source wirings to achieve LC balance, thereby reducing the skew between signal wirings and improving the quality of signal transfer.

Abstract translation: 提供一种具有共面LC平衡的印刷电路板，包括：绝缘层，形成在绝缘层上的印刷电路图案，在印刷电路图案中供电的电源布线以及形成在电源布线之间的至少三个信号布线， 其中远离电源布线的信号布线的宽度宽于与电源布线相邻的信号布线的宽度，以实现LC平衡，从而减少信号布线之间的偏斜并提高信号传输的质量。

公开(公告)号：US20080128883A1

公开(公告)日：2008-06-05

申请号：US11950990

申请日：2007-12-05

Applicant: Jong-Joo LEE

Inventor： Jong-Joo LEE

IPC: H01L23/36

CPC classification number: H01L23/481 ,  H01L23/3128 ,  H01L25/18 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06589 ,  H01L2924/15311

Abstract: Provided are a high I/O semiconductor chip package in which a processor and a memory device are connected to each other via through electrodes and a method of manufacturing the high I/O semiconductor chip package. The high I/O semiconductor chip package includes: a substrate comprising a plurality of first circuit patterns on a first surface and a plurality of second circuit patterns on a second surface; a first semiconductor chip comprising a plurality of memory devices arranged on the substrate, each memory device being arranged in a matrix in chip regions partitioned by a scribe region; a second semiconductor chip stacked on the first semiconductor chip; and a plurality of through electrodes arranged along peripheral portions of the memory devices and connecting the first and second semiconductor chips to the second circuit patterns of the substrate.

Abstract translation: 提供了一种高I / O半导体芯片封装，其中处理器和存储器件通过电极彼此连接，以及制造高I / O半导体芯片封装的方法。 高I ​​/ O半导体芯片封装包括：在第一表面上包括多个第一电路图案的基板和在第二表面上的多个第二电路图案; 第一半导体芯片，包括布置在所述基板上的多个存储器件，每个存储器件以矩阵布置在由划线区域分隔的芯片区域中; 堆叠在第一半导体芯片上的第二半导体芯片; 以及沿着存储装置的周边部分布置的多个通孔，并将第一和第二半导体芯片连接到基板的第二电路图案。

公开(公告)号：US20070278657A1

公开(公告)日：2007-12-06

申请号：US11710490

申请日：2007-02-26

Applicant: Jong-Joo Lee

Inventor： Jong-Joo Lee

IPC: H01L23/485 ,  H01L21/50 ,  H01L23/52

CPC classification number: H01L21/76898 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/17517 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73257 ,  H01L2224/81136 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/03 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A chip stack may include a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. Each semiconductor chip may have an active surface, a back surface opposite to the active surface, and a plurality of connection pads arranged in the center of the active surface. At least one through electrode may be formed in the first semiconductor chip and may be connected to at least one of the plurality of connection pads, and a portion of the at least one through electrode may be exposed by the back surface of the first semiconductor chip. The active surface of the first semiconductor chip may be arranged to face the active surface of the second semiconductor chip. The plurality of connection pads of the first semiconductor chip may be electrically connected to the plurality of connection pads of the second semiconductor chip.

Abstract translation: 芯片堆叠可以包括堆叠在第一半导体芯片上的第一半导体芯片和第二半导体芯片。 每个半导体芯片可以具有有源表面，与有源表面相对的后表面，以及布置在有源表面的中心的多个连接焊盘。 至少一个贯通电极可以形成在第一半导体芯片中并且可以连接到多个连接焊盘中的至少一个，并且至少一个贯通电极的一部分可以被第一半导体芯片的背面曝光 。 第一半导体芯片的有源表面可以布置成面对第二半导体芯片的有源表面。 第一半导体芯片的多个连接焊盘可以电连接到第二半导体芯片的多个连接焊盘。

公开(公告)号：US20070164429A1

公开(公告)日：2007-07-19

申请号：US11424605

申请日：2006-06-16

Applicant: Jong-Joo LEE

Inventor： Jong-Joo LEE

IPC: H01L23/48

CPC classification number: H01L23/50 ,  H01L23/49822 ,  H01L23/66 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05548 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/3011 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: A package board is provided. The package board includes a board body having a front surface and a back surface. A first power pad, a first ground pad, a first signal pad, a first internal terminal pad and a second internal terminal pad are disposed on the front surface of the board body, and a second power pad, a second ground pad and a second signal pad are disposed on the back surface of the board body. The second power pad, the second ground pad and the second signal pad are electrically connected to the first power pad, the first ground pad and the first signal pad, respectively. An internal terminal interconnection is provided in a bulk region of the board body or on a surface of the board body. The internal terminal interconnection electrically connects the first internal terminal pad to the second internal terminal pad. A semiconductor package employing the package board is also provided.

Abstract translation: 提供一个包装板。 封装板包括具有前表面和后表面的板体。 第一电源焊盘，第一接地焊盘，第一信号焊盘，第一内部端子焊盘和第二内部端子焊盘设置在板主体的前表面上，第二电源焊盘，第二接地焊盘和第二焊盘 信号垫设置在板体的背面。 第二电源焊盘，第二接地焊盘和第二信号焊盘分别电连接到第一电源焊盘，第一接地焊盘和第一信号焊盘。 内部端子互连设置在电路板主体的主体区域或电路板主体的表面上。 内部端子互连将第一内部端子焊盘电连接到第二内部端子焊盘。 还提供了采用封装板的半导体封装。