公开(公告)号：US09622339B2

公开(公告)日：2017-04-11

申请号：US13610663

申请日：2012-09-11

Applicant: Zhiguo Qian ,  Kemal Aygun

Inventor： Zhiguo Qian ,  Kemal Aygun

IPC: H05K1/02 ,  H05K3/46 ,  H05K1/11

CPC classification number: H05K1/0228 ,  H05K1/0219 ,  H05K1/0243 ,  H05K1/113 ,  H05K3/4644 ,  H05K2201/09336 ,  H05K2201/09672 ,  H05K2201/09709 ,  H05K2201/09727 ,  Y10T29/49155

Abstract: Certain embodiments relate to routing structures and their formation. In one embodiment a routing structure includes a first region including a first layer comprising alternating signal traces and ground traces separated by a dielectric. The first region also includes a second layer including alternating signal traces and ground traces separated by a dielectric, wherein the second layer signal positioned over the first layer ground traces, and the second layer ground traces positioned over the first layer signal traces. The first region may also include additional layers of alternating signal and ground traces. The first region may also be formed with the ground traces having a width that is larger than that of the signal traces. The routing structure may also include a second region including pads to which the traces are coupled. Other embodiments are described and claimed.

公开(公告)号：US20170034913A1

公开(公告)日：2017-02-02

申请号：US14811325

申请日：2015-07-28

Applicant: Infineon Technologies AG

Inventor： Qianli Mu ,  Cristian Gozzi ,  Michael Simcoe ,  Guillaume Bigny

IPC: H05K1/18 ,  H05K1/11 ,  H05K1/02

CPC classification number: H05K1/181 ,  H01L23/142 ,  H01L23/64 ,  H01L2224/49175 ,  H05K1/025 ,  H05K1/0298 ,  H05K1/111 ,  H05K1/115 ,  H05K1/144 ,  H05K1/182 ,  H05K3/421 ,  H05K3/429 ,  H05K2201/09236 ,  H05K2201/09327 ,  H05K2201/09336 ,  H05K2201/09481 ,  H05K2201/0959 ,  H05K2201/10166 ,  H05K2203/049

Abstract: A semiconductor package includes a metal baseplate, a semiconductor die having a reference terminal attached to the baseplate and an RF terminal facing away from the baseplate, and a multilayer circuit board having a first side attached to the baseplate and a second side facing away from the baseplate. The multilayer circuit board includes a plurality of interleaved signal and ground layers. One of the signal layers is at the second side of the multilayer circuit board and electrically connected to the RF terminal of the semiconductor die. One of the ground layers is at the first side of the multilayer circuit board and attached to the metal baseplate. Power distribution structures are formed in the signal layer at the second side of the multilayer circuit board. RF matching structures are formed in a different one of the signal layers than the power distribution structures.

Abstract translation: 半导体封装包括金属基板，具有附接到基板的参考端子的半导体管芯和远离基板的RF端子，以及多层电路板，其具有附接到基板的第一侧和远离基板的第二侧 底盘。 多层电路板包括多个交错信号和接地层。 信号层中的一个位于多层电路板的第二侧并电连接到半导体管芯的RF端子。 其中一个接地层位于多层电路板的第一侧并附着在金属底板上。 功率分配结构形成在多层电路板的第二侧的信号层中。 RF匹配结构形成在与功率分配结构不同的信号层中。

公开(公告)号：US09445492B2

公开(公告)日：2016-09-13

申请号：US13351108

申请日：2012-01-16

Applicant: Nan-Jang Chen ,  Hong-Chin Lin

Inventor： Nan-Jang Chen ,  Hong-Chin Lin

IPC: H05K1/16 ,  H05K1/02 ,  H05K3/22

CPC classification number: H05K1/0216 ,  H01L2924/0002 ,  H05K3/222 ,  H05K2201/0715 ,  H05K2201/093 ,  H05K2201/09336 ,  H05K2201/10363 ,  H05K2201/10515 ,  H05K2201/10689 ,  H01L2924/00

Abstract: A printed circuit board is disclosed. The printed circuit board comprises a substrate having a top surface and a bottom surface. A ground plane is on the bottom surface. A signal trace is on the top surface along a first direction. At least two isolated power planes are on the top surface adjacent to opposite sides of the signal trace, respectively. A conductive connection along a second direction couples to the two power planes, across the signal trace without electrically connecting to the signal trace, wherein the signal trace doesn't pass over any split of the ground plane.

Abstract translation: 公开了印刷电路板。 印刷电路板包括具有顶表面和底表面的基底。 地平面位于底面。 信号迹线沿着第一方向在顶表面上。 至少两个隔离的电源平面分别位于与信号迹线的相对侧相邻的顶表面上。 沿着第二方向的导电连接跨过信号迹线耦合到两个电源层，而不与电信号迹线电连接，其中信号迹线不经过接地平面的任何分裂。

公开(公告)号：US09386687B2

公开(公告)日：2016-07-05

申请号：US14367566

申请日：2012-12-20

Applicant: KYOCERA Corporation

Inventor： Mahiro Tsujino ,  Yoshiki Kawazu

IPC: H05K1/16 ,  H05K1/02 ,  H01L23/057 ,  H01L23/498 ,  H05K1/18

CPC classification number: H05K1/0213 ,  H01L23/057 ,  H01L23/49861 ,  H01L2224/48091 ,  H01L2924/3011 ,  H05K1/024 ,  H05K1/18 ,  H05K2201/09336 ,  H01L2924/00014 ,  H01L2924/00

Abstract: While it is necessary for an electronic component housing package to be provided with numerous wiring conductors, phase differences of signals caused by differences in signal transmission distance among the wiring conductors, is a problem. An electronic component housing package based on one embodiment includes a substrate having a dielectric region and an electronic component placement region, a frame body surrounding the dielectric region and the placement region, and wiring conductors disposed on the dielectric region of the substrate. The wiring conductors have a first wiring conductor and a second wiring conductor which is longer in signal transmission distance than the first wiring conductor, which are disposed so as to extend from a location immediately below the frame body to the dielectric region. The frame body made of a dielectric material has a projection protruding from its inner periphery, which covers at least part of the first wiring conductor.

Abstract translation: 虽然电子部件外壳封装需要多个布线导体，但是由布线导体之间的信号传输距离的差异引起的信号的相位差是一个问题。 基于一个实施例的电子部件壳体封装包括具有电介质区域和电子部件放置区域的基板，围绕介电区域和放置区域的框体，以及布置在基板的电介质区域上的布线导体。 所述布线导体具有第一布线导体和第二布线导体，所述第一布线导体和第二布线导体的信号传输距离比所述第一布线导体长，所述第一布线导体和所述第二布线导体被布置为从所述框体正下方的位置延伸到所述电介质 由介电材料制成的框架体具有从其内周突出的突起，其覆盖第一布线导体的至少一部分。

公开(公告)号：US09312216B2

公开(公告)日：2016-04-12

申请号：US14590291

申请日：2015-01-06

Applicant: Renesas Electronics Corporation

Inventor： Shuuichi Kariyazaki ,  Ryuichi Oikawa

IPC: H01L23/498 ,  H01L23/528 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L23/49822 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5225 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14131 ,  H01L2224/14135 ,  H01L2224/16057 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2924/1517 ,  H01L2924/15311 ,  H05K1/0225 ,  H05K1/0253 ,  H05K2201/09336 ,  H05K2201/09681 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00

Abstract: To improve noise immunity of a semiconductor device. A wiring substrate of a semiconductor device includes a first wiring layer where a wire is formed to which signals are sent, and a second wiring layer that is mounted adjacent to the upper layer or the lower layer of the first wiring layer. The second wiring layer includes a conductor plane where an aperture section is formed at a position overlapped with a portion of the wire 23 in the thickness direction, and a conductor pattern that is mounted within the aperture section of the conductor plane. The conductor pattern includes a main pattern section (mesh pattern section) that is isolated from the conductor plane, and plural coupling sections that couple the main pattern section and the conductor plane.

Abstract translation: 为了提高半导体器件的抗噪声性。 半导体器件的布线基板包括形成有信号发送线的第一布线层和与第一布线层的上层或下层相邻地安装的第二布线层。 第二布线层包括在厚度方向上与导线23的一部分重叠的位置处形成开口部的导体平面和安装在导体平面的开口部内的导体图案。 导体图案包括与导体平面隔离的主图案部分（网格图案部分）和耦合主图案部分和导体平面的多个耦合部分。

公开(公告)号：US09204533B2

公开(公告)日：2015-12-01

申请号：US13664358

申请日：2012-10-30

Applicant: Samsung Electro-Mechanics Co., Ltd.

Inventor： Romero Christian ,  Seung Wook Park ,  Young Do Kweon ,  Mi Jin Park

IPC: H03H7/38 ,  H05K3/00 ,  H05K1/02 ,  H05K1/16 ,  H05K3/46

CPC classification number: H05K1/0251 ,  H05K1/162 ,  H05K3/4602 ,  H05K2201/09336

Abstract: Disclosed herein are an asymmetrical multilayer substrate, an RF module, and a method for manufacturing the asymmetrical multilayer substrate. The asymmetrical multilayer substrate includes a core layer, a first pattern layer formed on one side of the core layer and including a first signal line pattern, a second pattern layer formed on the other side and including a second metal plate and a second routing line pattern, a first insulating layer thinner than the core layer formed on the second pattern layer and including a first via, and a third pattern layer formed on the first insulating layer and including a third signal line pattern, wherein an impedance transformation circuit including an impedance load and a parasitic capacitance load on the transmission line is formed for impedance matching in signal transmission between the signal line patterns formed in the upper and lower side directions of the core layer.

Abstract translation: 本文公开了不对称多层基板，RF模块和用于制造非对称多层基板的方法。 不对称多层基板包括芯层，形成在芯层的一侧上并包括第一信号线图案的第一图案层，形成在另一侧上的第二图案层，并且包括第二金属板和第二布线线图案 ，比形成在第二图案层上的芯层薄且包括第一通孔的第一绝缘层和形成在第一绝缘层上并包括第三信号线图案的第三图案层，其中阻抗变换电路包括阻抗负载 并且形成传输线上的寄生电容负载用于在形成在芯层的上侧和下侧方向上的信号线图案之间的信号传输中的阻抗匹配。

公开(公告)号：US09173292B1

公开(公告)日：2015-10-27

申请号：US13385859

申请日：2012-03-09

Applicant: Sergey Sokol ,  Ekrem Oran

Inventor： Sergey Sokol ,  Ekrem Oran

IPC: H05K1/11 ,  H05K3/32

CPC classification number: H05K1/117 ,  H05K1/0219 ,  H05K1/025 ,  H05K3/32 ,  H05K2201/09181 ,  H05K2201/09336 ,  H05K2201/09727 ,  H05K2201/10189 ,  H05K2201/10446

Abstract: An edge launch and fabrication method wherein spaced elongated slots are formed through a circuit board. The slots are plated at least along one side thereof connecting ground planes of the circuit board thus forming spaced edge plated regions. Circuit modules are produced by singulating the circuit board along a cut line offset outwardly from the plated slot sides to form an edge launch outwardly extending from and between the spaced edge plated regions.

Abstract translation: 边缘发射和制造方法，其中间隔的细长槽通过电路板形成。 这些槽至少沿着连接电路板的接地平面的一侧进行电镀，从而形成间隔开的边缘电镀区域。 电路模块通过沿着从电镀槽侧向外偏移的切割线分割电路板而产生，以形成从间隔边缘镀覆区域之间向外延伸的边缘发射。

公开(公告)号：US09118105B2

公开(公告)日：2015-08-25

申请号：US14557609

申请日：2014-12-02

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Noboru Kato ,  Jun Sasaki

IPC: H01Q7/08 ,  H01Q7/06 ,  H01L23/538 ,  H01L23/66 ,  H01Q1/20 ,  H01Q7/00 ,  H05K1/02 ,  H05K1/16 ,  H05K1/18 ,  H05K3/46

CPC classification number: H01Q7/06 ,  H01L23/5387 ,  H01L23/66 ,  H01L2223/6677 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01Q1/20 ,  H01Q1/38 ,  H01Q7/00 ,  H05K1/0233 ,  H05K1/0243 ,  H05K1/025 ,  H05K1/0281 ,  H05K1/165 ,  H05K1/189 ,  H05K3/4632 ,  H05K2201/05 ,  H05K2201/09336 ,  H05K2201/10098 ,  H05K2201/10189 ,  H01L2924/00

Abstract: A circuit board and a circuit module more accurately provide impedance matching between an antenna coil and an electronic component electrically connected to the antenna coil, and include a board body including board portions and a plurality of laminated insulating material layers made of a flexible material. An antenna coil includes coil conductors provided in the board portion. Wiring conductors are provided in the board portion and electrically connected to the antenna coil. The board portion has a structure that is less likely to deform than the board portion. An integrated circuit electrically connected to the wiring conductors is mounted on the board portion.

Abstract translation: 电路板和电路模块更准确地提供天线线圈和与天线线圈电连接的电子部件之间的阻抗匹配，并且包括板主体，其包括由柔性材料制成的板部分和多个层叠绝缘材料层。 天线线圈包括设置在板部分中的线圈导体。 配线导体设置在电路板部分中并电连接到天线线圈。 板部分具有不如板部分变形的结构。 电连接到布线导体的集成电路安装在基板部分上。

公开(公告)号：US09036364B1

公开(公告)日：2015-05-19

申请号：US12002361

申请日：2007-12-17

Applicant: Laurie P. Fung

Inventor： Laurie P. Fung

IPC: H05K1/02

CPC classification number: H05K1/0298 ,  H05K1/0243 ,  H05K1/025 ,  H05K2201/09336 ,  H05K2201/09727 ,  H05K2201/09972

Abstract: Electronic devices to output signals at different frequencies are mounted to a circuit board that has a group of layers, where the group of layers include reference plane layers and signal layers between the reference plane layers. A first signal layer has conductive traces having a first dimension to communicate the signals at a first frequency, and a second signal layer has conductive traces having a second, different dimension to communicate signals at a second, different frequency. The first and second signal layers are successive layers without any reference plane layer in between the first and second signal layers.

Abstract translation: 将以不同频率输出信号的电子设备安装到具有一组层的电路板，其中该组层包括参考平面层和参考平面层之间的信号层。 第一信号层具有导电迹线，其具有第一维度以在第一频率上传送信号，并且第二信号层具有导通迹线，具有第二不同维度以在第二不同频率传送信号。 第一和第二信号层是在第一和第二信号层之间没有任何参考平面层的连续层。

公开(公告)号：US20150029682A1

公开(公告)日：2015-01-29

申请号：US14379705

申请日：2013-02-08

Applicant: Hatachi Automotive Systems, Ltd

Inventor： Kiyoomi Kadoya ,  Ryosuke Ishida ,  Takuya Mayuzumi ,  Kenichi Hoshino ,  Yasuhiko Okada ,  Yasushi Sugiyama

IPC: H05K9/00 ,  H05K1/02

CPC classification number: H05K9/0064 ,  H05K1/0215 ,  H05K1/0218 ,  H05K1/0224 ,  H05K1/0298 ,  H05K5/006 ,  H05K9/0039 ,  H05K2201/09336 ,  H05K2201/10371

Abstract: Proposed is a C/U that is designed to accomplish the above object. The CU includes a multilayer circuit substrate, a resin cover, and a metal base. Electronic parts are mounted on both surfaces of the multilayer circuit substrate which is covered with the resin cover and the metal base. The multilayer circuit substrate 8 includes a signal pattern, a GND pattern, an important signal pattern, and a multilayer circuit substrate insulating layer. The GND pattern is electrically connected to the metal base through a screw. The GND pattern is disposed on the side of the resin cover in order to shield the important signal pattern against electromagnetic waves penetrating the resin cover to enter a housing and electromagnetic waves incident from the metal base side. The important signal pattern is disposed so that it is covered with the GND pattern and the metal case.

Abstract translation: 建议设计用于实现上述目的的C / U。 CU包括多层电路基板，树脂盖和金属基座。 电子部件安装在被树脂盖和金属基底覆盖的多层电路基板的两个表面上。 多层电路衬底8包括信号图案，GND图案，重要信号图案和多层电路衬底绝缘层。 GND图案通过螺丝与金属基座电连接。 GND图案设置在树脂盖的侧面上，以便屏蔽重要信号图案以抵抗穿过树脂盖的电磁波进入外壳和从金属基座侧入射的电磁波。 重要信号图案被布置成使其被GND图案和金属外壳覆盖。