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    Low height type actuator capable of performing a two-dimension motion
    41.
    发明授权
    Low height type actuator capable of performing a two-dimension motion 有权

    公开(公告)号：US11557953B2

    公开(公告)日：2023-01-17

    申请号：US16071366

    申请日：2017-01-19

    Applicant: TDK CORPORATION ,  TOKYO INSTITUTE OF TECHNOLOGY

    Inventor： Kenichi Suzuki ,  Tadahiko Shinshi ,  Ryogen Fujiwara

    IPC: H02K41/02 ,  H02K41/03 ,  G02B27/64 ,  G03B5/00

    Abstract: A low height type actuator capable of performing a two-dimensional motion includes a magnet structure that includes a first array in which the first and second magnets are alternately arranged in x-direction and a second array in which the first and second magnets are alternately arranged in y-direction, and first and second wirings. The first wiring crosses the first magnets included in the first array in y-direction, and the second wiring crosses the first magnets included in the second array in x-direction. According to the present invention, by making current flow in the first and second wirings, a two-dimensional motion can be achieved. Further, since the first and second wirings are each a planar wiring that crosses the magnets, height reduction can be achieved.

    NON-VOLATILE STORAGE DEVICE, NON-VOLATILE STORAGE ELEMENT, AND MANUFACTURING METHOD FOR THEIR PRODUCTION
    43.
    发明申请
    NON-VOLATILE STORAGE DEVICE, NON-VOLATILE STORAGE ELEMENT, AND MANUFACTURING METHOD FOR THEIR PRODUCTION 有权

    公开(公告)号：US20230012093A1

    公开(公告)日：2023-01-12

    申请号：US17781803

    申请日：2020-12-04

    Applicant: Tokyo Institute of Technology

    Inventor： Kuniyuki KAKUSHIMA ,  Hiroshi FUNAKUBO ,  Shun-ichiro OHMI ,  Joel MOLINA REYES ,  Ichiro FUJIWARA ,  Atsushi HORI ,  Takao SHIMIZU ,  Yoshiko NAKAMURA ,  Takanori MIMURA

    IPC: H01L27/11502 ,  H01L27/11585 ,  H01L27/11 ,  G11C11/22 ,  H01L27/11524

    Abstract: The invention provides a non-volatile storage element and non-volatile storage device employing a ferroelectric material with low power consumption, excellent high reliability, and especially write/erase endurance, which can be mixed with advanced CMOS logic. The non-volatile storage element has at least a first conductive layer, a second conductive layer, and a ferroelectric layer composed of a metal oxide between both conductive layers, with a buffer layer having oxygen ion conductivity situated between the ferroelectric layer and the first conductive layer and/or second conductive layer. An interface layer composed of a single-layer film or a multilayer film may be also provided between the first conductive layer and the ferroelectric layer, the interface layer as a whole having higher dielectric constant than silicon oxide, and when the buffer layer is present between the first conductive layer and the ferroelectric layer, the interface layer is situated between the first conductive layer and the buffer layer. The non-volatile storage device comprises at least a memory cell array comprising low-power-consumption ferroelectric memory elements formed in a two-dimensional or three-dimensional configuration, and a control circuit. The ferroelectric layer is scalable to 10 nm or smaller and is fabricated at a low temperature of ≤400° C., and is subjected to low temperature thermal annealing treatment at ≤400° C. after the buffer layer has been formed, to provide high reliability.

    Cell evaluation device and cell evaluation system
    45.
    发明授权
    Cell evaluation device and cell evaluation system 有权

    公开(公告)号：US11549092B2

    公开(公告)日：2023-01-10

    申请号：US16689820

    申请日：2019-11-20

    Applicant: Shimadzu Corporation ,  Tokyo Institute of Technology

    Inventor： Yoichi Fujiyama ,  Chikara Miyake ,  Yoh-ichi Tagawa

    IPC: B01L3/00 ,  C12M1/00

    Abstract: A cell evaluation device includes: a porous membrane having a first main face and a second main face; a first passage having a first passage portion facing a first area on which cells are placed in the first main face of the porous membrane; a second passage having a second passage portion facing a second area in the second main face of the porous membrane, the second area being positioned backside of the first area; and a first electrode provided in the first passage portion and a second electrode provided in the second passage portion, the first electrode and the second electrode being positioned across the first area and the second area. In the cell evaluation device, tight junctions are formed among the cells by cell cultivation. With the cell evaluation device, any increase in the electric resistance occurring due to the formation of the tight junctions can be easily measured.

    ASYMMETRICALLY BRANCHED DEGRADABLE POLYETHYLENE GLYCOL DERIVATIVE
    47.
    发明申请
    ASYMMETRICALLY BRANCHED DEGRADABLE POLYETHYLENE GLYCOL DERIVATIVE 有权

    公开(公告)号：US20220339290A1

    公开(公告)日：2022-10-27

    申请号：US17763516

    申请日：2020-09-25

    Applicant: NOF CORPORATION ,  TOKYO INSTITUTE OF TECHNOLOGY

    Inventor： Ken Hamura ,  Hiroki Yoshioka ,  Kazuki Osakama ,  Nobuhiro Nishiyama

    IPC: A61K47/64 ,  A61K47/60

    Abstract: A branched degradable polyethylene glycol derivative with a high molecular weight that does not cause vacuolation of cells is provided. A branched degradable polyethylene glycol derivative represented by the following formula (1), containing, in a molecule, an oligopeptide that is degraded in the cells: wherein k1 and k2 are each independently 1-12, j1 and j2 are each independently 45-950, R is a hydrogen atom, a substituted or unsubstituted alkyl group having 1-12 carbon atoms, a substituted aryl group, an aralkyl group or a heteroalkyl group, Z is an oligopeptide that is degraded by enzyme in the cells, X is a functional group capable of reacting with a bio-related substance, and L1 and L2 are each independently a single bond or a divalent spacer.

    Semiconductor device and control method thereof
    48.
    发明授权
    Semiconductor device and control method thereof 有权

    公开(公告)号：US11456028B2

    公开(公告)日：2022-09-27

    申请号：US17191752

    申请日：2021-03-04

    Applicant: HONDA MOTOR CO., LTD. ,  TOKYO INSTITUTE OF TECHNOLOGY

    Inventor： Koji Sakui ,  Takayuki Ohba

    IPC: G11C11/408 ,  G11C11/4096 ,  H01L23/48 ,  H01L25/18

    Abstract: A semiconductor device according to the present invention is formed by a plurality of semiconductor chips laminated on a substrate which are connected via a through electrode penetrating in a lamination direction, in which the plurality of semiconductor chips include first semiconductor chips 104 each having memory blocks and a decoder and a second semiconductor chip having a logic circuit, the logic circuit includes one selection circuit connected to the decoder of all the first semiconductor chips 104 and configured to select addresses of a first memory block 106A that stops input/output and a second memory block 106B that performs input/output instead among the plurality of memory blocks, and the addresses of the selected first memory block 106A and the selected second memory block 106B are each common to all the first semiconductor chips.

    Semiconductor device
    50.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11437349B2

    公开(公告)日：2022-09-06

    申请号：US17147658

    申请日：2021-01-13

    Applicant: HONDA MOTOR CO., LTD. ,  TOKYO INSTITUTE OF TECHNOLOGY

    Inventor： Koji Sakui ,  Takayuki Ohba

    IPC: H01L25/065 ,  H01L25/18 ,  H01L23/48 ,  G11C5/06 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4097

    Abstract: This semiconductor device includes a memory semiconductor chip having a plurality of memory cells, a planar buffer chip which is a semiconductor chip that comprises a plurality of buffer circuits which hold data read from the memory cell and data written to the memory cell and which output the held data in accordance with the number of bit lines of the plurality of memory cells, an electrical connection structure which electrically connects the bit lines of the memory cells of the memory semiconductor chip and the buffer circuits of the planar buffer chip to each other in a thickness direction of the memory semiconductor chip and the planar buffer chip, and a plurality of bit wiring layers provided in accordance with the respective buffer circuits and electrically connected to the bit lines of the buffer circuits. The bit wiring layers are laminated on the planar buffer chip.

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