公开(公告)号：US11797473B2

公开(公告)日：2023-10-24

申请号：US16154517

申请日：2018-10-08

Applicant: ALTERA CORPORATION

Inventor： David Shippy ,  Martin Langhammer ,  Jeffrey Eastlack

IPC: G06F15/78 ,  G06F9/30 ,  G06F9/38 ,  G06F13/28 ,  G06F9/54 ,  G06F17/14 ,  G06F13/12

CPC classification number: G06F15/7825 ,  G06F9/30036 ,  G06F9/3877 ,  G06F9/3887 ,  G06F9/541 ,  G06F13/124 ,  G06F13/28 ,  G06F17/142

Abstract: An accelerated processor structure on a programmable integrated circuit device includes a processor and a plurality of configurable digital signal processors (DSPs). Each configurable DSP includes a circuit block, which in turn includes a plurality of multipliers. The accelerated processor structure further includes a first bus to transfer data from the processor to the configurable DSPs, and a second bus to transfer data from the configurable DSPs to the processor.

公开(公告)号：US10678510B2

公开(公告)日：2020-06-09

申请号：US16333970

申请日：2017-09-25

Applicant: Altera Corporation

Inventor： Martin Langhammer

IPC: G06F7/57 ,  G06F7/483 ,  G06F7/487 ,  G06F7/499 ,  G06F7/544

Abstract: The present embodiments relate to integrated circuits with floating-point arithmetic circuitry that handles normalized and denormalized floating-point numbers. The floating-point arithmetic circuitry may include a normalization circuit and a rounding circuit, and the floating-point arithmetic circuitry may generate a first result in form of a normalized, unrounded floating-point number and a second result in form of a normalized, rounded floating-point number. If desired, the floating-point arithmetic circuitry may be implemented in specialized processing blocks.

公开(公告)号：US20190250886A1

公开(公告)日：2019-08-15

申请号：US16333970

申请日：2017-09-25

Applicant: Altera Corporation

Inventor： Martin Langhammer

IPC: G06F7/57 ,  G06F7/483 ,  G06F7/499

Abstract: The present embodiments relate to integrated circuits with floating-point arithmetic circuitry that handles normalized and denormalized floating-point numbers. The floating-point arithmetic circuitry may include a normalization circuit and a rounding circuit, and the floating-point arithmetic circuitry may generate a first result in form of a normalized, unrounded floating-point number and a second result in form of a normalized, rounded floating-point number. If desired, the floating-point arithmetic circuitry may be implemented in specialized processing blocks.

公开(公告)号：US20180341460A1

公开(公告)日：2018-11-29

申请号：US16056173

申请日：2018-08-06

Applicant: ALTERA CORPORATION

Inventor： Martin Langhammer

IPC: G06F7/485 ,  G06F7/505 ,  G06F5/01 ,  G06F5/16 ,  G06F7/483

CPC classification number: G06F7/485 ,  G06F5/012 ,  G06F5/16 ,  G06F7/483 ,  G06F7/505 ,  G06F2207/3824

Abstract: The present embodiments relate to circuitry that efficiently performs floating-point arithmetic operations and fixed-point arithmetic operations. Such circuitry may be implemented in specialized processing blocks. If desired, the specialized processing blocks may include configurable interconnect circuitry to support a variety of different use modes. For example, the specialized processing block may efficiently perform a fixed-point or floating-point addition operation or a portion thereof, a fixed-point or floating-point multiplication operation or a portion thereof, a fixed-point or floating-point multiply-add operation or a portion thereof, just to name a few. In some embodiments, two or more specialized processing blocks may be arranged in a cascade chain and perform together more complex operations such as a recursive mode dot product of two vectors of floating-point numbers or a Radix-2 Butterfly circuit, just to name a few.

公开(公告)号：US20180241415A1

公开(公告)日：2018-08-23

申请号：US15958623

申请日：2018-04-20

Applicant: Altera Corporation

Inventor： Martin Langhammer

IPC: H03M13/15

CPC classification number: H03M13/1595 ,  H03M13/157 ,  H03M13/1575 ,  H03M13/159

Abstract: Syndrome calculation circuitry for a decoder of codewords having a first number of symbols, where the decoder receives a second number of parallel symbols, and where the first number is not evenly divisible by the second number, includes multipliers equal in number to the second number. Each multiplier multiplies a symbol by a coefficient based on a root of a field of the decoder. The multipliers are divided into a number of groups determined as a function of a modulus of the first number and the second number. Adders equal in number to the groups add outputs of multipliers in respective ones of the groups. Accumulation circuitry accumulates outputs of the adders. Output circuitry adds outputs of the adders to an output of the accumulation circuitry to provide a syndrome. Selection circuitry directs outputs of the adders to the accumulation circuitry or the output circuitry, and resets the accumulation circuitry.

公开(公告)号：US10042607B2

公开(公告)日：2018-08-07

申请号：US15242923

申请日：2016-08-22

Applicant: Altera Corporation

Inventor： Martin Langhammer

IPC: G06F7/485 ,  G06F7/487

Abstract: Integrated circuits with specialized processing blocks are provided. The specialized processing blocks may include floating-point multiplier circuits that can be configured to support variable precision. A multiplier circuit may include a first carry-propagate adder (CPA), a second carry-propagate adder (CPA), and an associated rounding circuit. The first CPA may be wide enough to handle the required precision of the mantissa. In a bridged mode, the first CPA may borrow an additional bit from the second CPA while the rounding circuit will monitor the appropriate bits to select the proper multiplier output. A parallel prefix tree operable in a non-bridged mode or the bridged mode may be used to compute multiple multiplier outputs. The multiplier circuit may also include exponent and exception handling circuitry using various masks corresponding to the desired precision width.

公开(公告)号：US20180081631A1

公开(公告)日：2018-03-22

申请号：US15270153

申请日：2016-09-20

Applicant: Altera Corporation

Inventor： Martin Langhammer

IPC: G06F7/487

CPC classification number: G06F7/4876

Abstract: The present embodiments relate to circuitry that efficiently performs double-precision floating-point multiplication operations, single-precision floating-point multiplication operations, and fixed-point multiplication operations. Such circuitry may be implemented in specialized processing blocks. If desired, each specialized processing block efficiently may perform a single-precision floating-point multiplication operation, and multiple specialized processing blocks may be coupled together to perform a double-precision floating-point multiplication operation. Inter-block signaling circuits may generate rounding information and propagate the rounding information together with partial product results from a current specialized processing block to another specialized processing block.

公开(公告)号：US20180006664A1

公开(公告)日：2018-01-04

申请号：US15197433

申请日：2016-06-29

Applicant: Altera Corporation

Inventor： Martin Langhammer ,  Simon Finn ,  Sami Mumtaz

IPC: H03M13/15 ,  H03M13/00

Abstract: An integrated circuit for implementing a Reed-Solomon encoder circuit is provided. The encoder circuit may include partial syndrome calculation circuitry and matrix multiplication circuitry. The partial syndrome calculation circuitry may receive a message and generate corresponding partial syndromes. The matrix multiplication circuitry may receive the partial syndromes and may compute parity check symbols by multiplying the partial syndromes by predetermined Lagrangian polynomial coefficients. The parity check symbol generation step may be performed in one clock cycle or multiple clock cycles.

公开(公告)号：US09684488B2

公开(公告)日：2017-06-20

申请号：US14669288

申请日：2015-03-26

Applicant: Altera Corporation

Inventor： Martin Langhammer

IPC: G06F7/505 ,  G06F7/49 ,  G06F7/53 ,  G06F7/501

CPC classification number: G06F7/49 ,  G06F7/501 ,  G06F7/5312

Abstract: Circuitry accepting a first input value and a second input value, and outputting (a) a first sum involving the first input value and the second input value, and (b) a second sum involving the first input value and the second input value, includes a first adder circuit, a second adder circuit, a compressor circuit and a preprocessing stage. The first input value and the second input value are input to the first adder circuit to provide the first sum. The first input value and the second input value are input to the preprocessing stage to provide inputs to the compressor circuit, which provides first and second compressed output signals which in turn are input to the second adder circuit to provide the second sum. The preprocessing stage may include circuitry to programmably zero the first input value, so that the first sum is programmably settable to the second input value.

公开(公告)号：US20170115958A1

公开(公告)日：2017-04-27

申请号：US14919429

申请日：2015-10-21

Applicant: Altera Corporation

Inventor： Martin Langhammer

IPC: G06F7/523

CPC classification number: G06F7/523 ,  G06F7/5443 ,  G06F7/57

Abstract: A specialized processing block on an integrated circuit includes a first and second arithmetic operator stage, an output coupled to another specialized processing block, and configurable interconnect circuitry which may be configured to route signals throughout the specialized processing block, including in and out of the first and second arithmetic operator stages. The configurable interconnect circuitry may further include multiplexer circuitry to route selected signals. The output of the specialized processing block that is coupled to another specialized processing block together with the configurable interconnect circuitry reduces the need to use resources outside the specialized processing block when implementing mathematical functions that require the use of more than one specialized processing block. An example for such mathematical functions include the implementation of scaled product sum operations and the implementation of Horner's rule.