公开(公告)号：US20190065188A1

公开(公告)日：2019-02-28

申请号：US16154517

申请日：2018-10-08

Applicant: ALTERA CORPORATION

Inventor： David Shippy ,  Martin Langhammer ,  Jeffrey Eastlack

IPC: G06F9/30 ,  G06F9/38 ,  G06F13/28 ,  G06F17/50 ,  G06F17/14 ,  G06F9/54

Abstract: An accelerated processor structure on a programmable integrated circuit device includes a processor and a plurality of configurable digital signal processors (DSPs). Each configurable DSP includes a circuit block, which in turn includes a plurality of multipliers. The accelerated processor structure further includes a first bus to transfer data from the processor to the configurable DSPs, and a second bus to transfer data from the configurable DSPs to the processor.

公开(公告)号：US20240078211A1

公开(公告)日：2024-03-07

申请号：US18368492

申请日：2023-09-14

Applicant: Altera Corporation

Inventor： David Shippy ,  Martin Langhammer ,  Jeffrey Eastlack

IPC: G06F15/78 ,  G06F9/30 ,  G06F9/38 ,  G06F9/54 ,  G06F13/12 ,  G06F13/28 ,  G06F17/14

CPC classification number: G06F15/7825 ,  G06F9/30036 ,  G06F9/3877 ,  G06F9/3887 ,  G06F9/541 ,  G06F13/124 ,  G06F13/28 ,  G06F17/142

Abstract: An accelerated processor structure on a programmable integrated circuit device includes a processor and a plurality of configurable digital signal processors (DSPs). Each configurable DSP includes a circuit block, which in turn includes a plurality of multipliers. The accelerated processor structure further includes a first bus to transfer data from the processor to the configurable DSPs, and a second bus to transfer data from the configurable DSPs to the processor.

公开(公告)号：US10095647B2

公开(公告)日：2018-10-09

申请号：US14725811

申请日：2015-05-29

Applicant: Altera Corporation

Inventor： David Shippy ,  Martin Langhammer ,  Jeffrey Eastlack

IPC: G06F9/30 ,  G06F13/40 ,  G06F13/42

Abstract: An accelerated processor structure on a programmable integrated circuit device includes a processor and a plurality of configurable digital signal processors (DSPs). Each configurable DSP includes a circuit block, which in turn includes a plurality of multipliers. The accelerated processor structure further includes a first bus to transfer data from the processor to the configurable DSPs, and a second bus to transfer data from the configurable DSPs to the processor.

公开(公告)号：US11797473B2

公开(公告)日：2023-10-24

申请号：US16154517

申请日：2018-10-08

Applicant: ALTERA CORPORATION

Inventor： David Shippy ,  Martin Langhammer ,  Jeffrey Eastlack

IPC: G06F15/78 ,  G06F9/30 ,  G06F9/38 ,  G06F13/28 ,  G06F9/54 ,  G06F17/14 ,  G06F13/12

CPC classification number: G06F15/7825 ,  G06F9/30036 ,  G06F9/3877 ,  G06F9/3887 ,  G06F9/541 ,  G06F13/124 ,  G06F13/28 ,  G06F17/142

Abstract: An accelerated processor structure on a programmable integrated circuit device includes a processor and a plurality of configurable digital signal processors (DSPs). Each configurable DSP includes a circuit block, which in turn includes a plurality of multipliers. The accelerated processor structure further includes a first bus to transfer data from the processor to the configurable DSPs, and a second bus to transfer data from the configurable DSPs to the processor.

公开(公告)号：US20150347338A1

公开(公告)日：2015-12-03

申请号：US14725811

申请日：2015-05-29

Applicant: ALTERA CORPORATION

Inventor： David Shippy ,  Martin Langhammer ,  Jeffrey Eastlack

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4027 ,  G06F13/4221

Abstract: An accelerated processor structure on a programmable integrated circuit device includes a processor and a plurality of configurable digital signal processors (DSPs). Each configurable DSP includes a circuit block, which in turn includes a plurality of multipliers. The accelerated processor structure further includes a first bus to transfer data from the processor to the configurable DSPs, and a second bus to transfer data from the configurable DSPs to the processor.

Abstract translation: 可编程集成电路器件上的加速处理器结构包括处理器和多个可配置的数字信号处理器（DSP）。 每个可配置DSP包括电路块，该电路块又包括多个乘法器。 加速处理器结构还包括将数据从处理器传送到可配置DSP的第一总线，以及将数据从可配置DSP传输到处理器的第二总线。