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公开(公告)号：US12062248B2
公开(公告)日：2024-08-13
申请号：US18009220
申请日：2021-05-25
Applicant: BOE Technology Group Co., Ltd.
Inventor： Changfeng Li , Xiaochuan Chen , Fuqiang Li , Liwei Liu , Hongrun Wang , Hui Zhang , Shunhang Zhang , Kai Hou , Yunsik Im , Yunping Di
IPC: G06V40/13 , G02F1/1335 , G02F1/1362 , G02F1/1368
CPC classification number: G06V40/1318 , G02F1/136209 , G02F1/136222 , G02F1/136286 , G02F1/1368
Abstract: A display panel and a display device are provided. The display panel has a touch side and includes an array substrate and an opposite substrate arranged opposite to each other. The array substrate includes an image sensor array including a plurality of image sensors each including a photosensitive element configured to receive light reflected by a texture touched on the touch side for texture acquisition; the opposite substrate includes a light shielding layer including a plurality of first openings arranged in an array, and the plurality of first openings are in one-to-one correspondence with and partially overlap with the photosensitive elements of the plurality of image sensors in a direction perpendicular to a panel surface of the display panel.
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公开(公告)号：US20240194698A1
公开(公告)日：2024-06-13
申请号：US17772395
申请日：2021-06-29
Applicant: BOE Technology Group Co., Ltd.
Inventor： Lizhong Wang , Ce Ning , Yunping Di , Binbin Tong , Zhen Zhang , Zhenyu Zhang , Fuqiang Li , Chengfu Xu
IPC: H01L27/12
CPC classification number: H01L27/1251 , H01L27/1222 , H01L27/124 , H01L27/127
Abstract: A displaying base plate and a manufacturing method thereof, and a displaying device. The displaying base plate includes an active area and a non-active area located at the periphery of the active area, wherein the active area includes an opening area and a non-opening area. The displaying base plate includes a substrate and a thin-film transistor disposed on one side of the substrate, wherein the thin-film transistor includes a grid electrode, an active layer, a source-drain electrode and an auxiliary film layer, an excavation area is disposed on the auxiliary film layer, and an orthographic projection of the excavation area on the substrate at least partially covers the opening area.
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43.发明公开公开(公告)号：US20240012290A1
公开(公告)日：2024-01-11
申请号：US18472236
申请日：2023-09-22
Applicant: BOE Technology Group Co., Ltd.
Inventor： Ming Yang , Yanan Niu , Fuqiang Li , Qi Qi , Wanzhi Chen , Zhenyu Zhang , Changfeng Li
IPC: G02F1/1335 , G09G3/34
CPC classification number: G02F1/133616 , G09G3/3426 , G02F2203/02 , G09G2310/0202 , G09G2320/0233 , H01L25/0753
Abstract: A light emitting substrate is provided. The light emitting substrate includes at least one light emitting controlling unit. The at least one light emitting controlling unit includes a plurality of light emitting elements arranged in M rows and N columns and grouped into (P×Q) number of sub-units, M being an integer equal to or greater than one, N being an integer equal to or greater than one, P being an integer equal to or greater than one, and Q being an integer equal to or greater than one; P groups of first voltage signal lines; and Q groups of second voltage signal lines. The (P×Q) number of sub-units are arranged in P rows and Q columns. A respective sub-unit in a p-th row and a q-th column includes K columns of light emitting elements, K being an integer equal to or greater than one.
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44.发明公开公开(公告)号：US20230154385A1
公开(公告)日：2023-05-18
申请号：US17631586
申请日：2021-03-04
Applicant: BOE Technology Group Co., Ltd.
Inventor： Ming Yang , Fuqiang Li , Xingce Shang , Wei Hao , Lin Zhou , Qi Qi
IPC: G09G3/32 , H01L25/075 , H01L33/62
CPC classification number: G09G3/32 , H01L25/0753 , H01L33/62 , H01L24/05
Abstract: A light emitting substrate is provided. The light emitting substrate includes a plurality of light emitting controlling units arranged in M rows and N columns, M is an integer equal to or greater than one, N is an integer equal to or greater than one. A respective column of the N columns of light emitting controlling units includes M number of groups of second voltage signal lines, a respective group of the M number of groups of second voltage signal lines connected to a respective one of the M number of light emitting controlling units, the respective group of the M number of groups of second voltage signal lines including k number of second voltage signal lines, k is an integer equal to or greater than one.
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45.发明授权公开(公告)号：US11636800B2
公开(公告)日：2023-04-25
申请号：US17489612
申请日：2021-09-29
Applicant: BOE Technology Group Co., Ltd.
Inventor： Lubin Shi , Fuqiang Li , Tingting Zhou
Abstract: A pixel circuit includes: a charge storage circuit with first and second terminals thereof electrically coupled to first and second nodes, respectively; a reset circuit with first, second and third control terminals thereof electrically coupled to a reference signal line, a first initialization signal line, and a second initialization signal line, respectively, with fourth, fifth and sixth terminals thereof electrically coupled to the first node, a cathode of a photodiode and the second node, respectively; a photosensitive control circuit with first, second and third terminals thereof electrically coupled to an anode of the photodiode, the first node and the second node, respectively; an output circuit with first and second terminals thereof electrically coupled to a first level terminal and a fourth terminal of the photosensitive control circuit, respectively.
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Patent Agency Ranking
公开(公告)号：US11538385B2
公开(公告)日：2022-12-27
申请号：US17355858
申请日：2021-06-23
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Zhichong Wang , Guangcai Yuan , Fuqiang Li , Jing Feng , Xinglong Luan , Peng Liu
IPC: G09G3/20 , G09G3/36 , G09G3/3266 , G06F3/041
Abstract: A gate driving unit includes: a pull-up node denoising circuit; a pull-down node control circuit; a pull-up node control circuit; and an energy storage circuit. The pull-up node denoising circuit is configured to, under control of a potential of the pull-down node, control coupling or discoupling between the first pull-up node and the input terminal. The pull-down node control circuit is configured to, under control of a control voltage, control the potential of the pull-down node; under control of a potential of the second pull-up node, control coupling or discoupling between the pull-down node and the input terminal. The pull-up node control circuit is configured to, under control of an anti-leakage control voltage, control coupling or discoupling between the first pull-up node and the second pull-up node, and configured to maintain the potential of the second pull-up node. The energy storage circuit is configured to store electric energy.
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公开(公告)号：US20220293635A1
公开(公告)日：2022-09-15
申请号：US17529969
申请日：2021-11-18
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Chenyang Zhang , Fuqiang Li , Xue Dong , Meili Wang , Xuan Liang , Fei Wang , Mingxing Wang , Zhanfeng Cao , Yanling Han , Xinxin Zhao
IPC: H01L27/12
Abstract: A semiconductor apparatus and a method for manufacturing the semiconductor apparatus are provided. The semiconductor apparatus includes: a base substrate; a plurality of chips arranged on the base substrate each including a chip main body and a plurality of terminals arranged thereon; a plurality of fixed connection portions arranged on the base substrate, and adjacent to the plurality of chips; a terminal expansion layer arranged on the base substrate; and a plurality of expansion wires in the terminal expansion layer and configured to electrically connect the chips, wherein an expansion wire configured to electrically connect two chips includes at least a first wire segment and a second wire segment, and the first wire segment is configured to electrically connect a terminal of a chip and a fixed connection portion adjacent to the chip, and the second wire segment is configured to connect two fixed connection portions between the two chips.
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公开(公告)号：US11409202B2
公开(公告)日：2022-08-09
申请号：US17199395
申请日：2021-03-11
Applicant: BOE Technology Group Co., Ltd.
Inventor： Xinglong Luan , Fuqiang Li , Jing Feng , Zhichong Wang , Peng Liu , Guangcai Yuan , Xue Dong
Abstract: Provided is a digital exposure control method, including: performing exposure of different types of functional areas of a substrate to be exposed through one or a plurality of full-page scans, wherein scan speeds for different types of functional areas of the substrate to be exposed are different.
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49.发明授权公开(公告)号：US11385732B2
公开(公告)日：2022-07-12
申请号：US16338288
申请日：2018-10-24
Inventor： Mingchao Ma , Jun Fan , Fuqiang Li
IPC: G06F3/041
Abstract: The present disclosure relates to the field of touch display technologies, and provides an array substrate, a manufacturing method thereof, a touch display panel and a touch display device. The array substrate includes a base substrate, and a plurality of thin film transistors, an insulating planarization layer, a plurality of pixel electrodes, a plurality of touch electrodes and a plurality of common electrodes formed sequentially on the base substrate. The insulating planarization layer has a plurality of vias exposing a drain of each thin film transistor respectively. Each pixel electrode is connected to a drain of a corresponding thin film transistor through a via in the insulating planarization layer, and each common electrode is connected to a corresponding touch electrode.
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50.发明授权公开(公告)号：US11282470B2
公开(公告)日：2022-03-22
申请号：US16327704
申请日：2018-08-01
Inventor： Yishan Fu , Jun Fan , Han Zhang , Fuqiang Li
Abstract: This disclosure discloses a shift register element, a method for driving the same, a gate driver circuit, and a display device. The shift register element comprises a first input circuit, a second input circuit, a first node control circuit, a second node control circuit, a third node control circuit, and N output circuits, where the first input circuit, the second input circuit, and the first node control circuit are configured to control a first node, the second node control circuit is configured to control a second node so that the third node control circuit controls the third node according to the first node and the second node, and the N output circuits control corresponding output terminals according to corresponding clock signal terminals under the control of the first node.
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