公开(公告)号：US20230317740A1

公开(公告)日：2023-10-05

申请号：US18021090

申请日：2022-03-04

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Lizhong Wang ,  Ce Ning ,  Yunping Di ,  Binbin Tong ,  Rui Huang ,  Tianmin Zhou ,  Wei Yang ,  Liping Lei

IPC: H01L27/12 ,  G02F1/1362 ,  G02F1/1368

CPC classification number: H01L27/1251 ,  H01L27/1225 ,  H01L27/124 ,  G02F1/136209 ,  G02F1/136286 ,  G02F1/1368 ,  H01L27/127

Abstract: The present application provides an array substrate, a manufacturing method for the same, and a display panel. The array substrate includes a display area and a non-display area connected to the display area, and the display area includes a plurality of sub-pixels arranged in an array. The non-display area includes at least one polysilicon transistor, each of the sub-pixels includes an oxide transistor and a pixel electrode. A gate of the oxide transistor as well as a first electrode and a second electrode of the polysilicon transistor are arranged in a same layer; an active layer of the oxide transistor and the pixel electrode are arranged in a same layer, and are in contact with each other. The active layer of the oxide transistor includes an oxide semiconductor material, and the pixel electrode includes an oxide conductor material.

公开(公告)号：US20250164843A1

公开(公告)日：2025-05-22

申请号：US19027233

申请日：2025-01-17

Applicant: BOE Technology Group Co., Ltd.

Inventor： Zhen Zhang ,  Fuqiang Li ,  Zhenyu Zhang ,  Yunping Di ,  Lizhong Wang ,  Zheng Fang ,  Jiahui Han ,  Yawei Wang ,  Chenyang Zhang ,  Chengfu Xu ,  Ce Ning ,  Pengxia Liang ,  Feihu Zhou ,  Xianqin Meng ,  Weiting Peng ,  Qiuli Wang ,  Binbin Tong ,  Rui Huang ,  Tianmin Zhou ,  Wei Yang

IPC: G02F1/1368 ,  G02F1/1362 ,  H10D86/01 ,  H10D86/40 ,  H10D86/60

Abstract: A displaying base plate and a displaying device are provided by the present application, wherein the displaying base plate includes a substrate, and a first electrode layer disposed on one side of the substrate, wherein the first electrode layer includes a first electrode pattern; a first planarization layer disposed on one side of the first electrode layer that is away from the substrate, wherein the first planarization layer is provided with a through hole, and the through hole penetrates the first planarization layer, to expose the first electrode pattern; and a second electrode layer, a second planarization layer and a third electrode layer that are disposed in stack on one side of the first planarization layer that is away from the substrate.

公开(公告)号：US12235558B2

公开(公告)日：2025-02-25

申请号：US18017413

申请日：2022-03-31

Applicant: BOE Technology Group Co., Ltd.

Inventor： Yunping Di ,  Lizhong Wang ,  Ce Ning ,  Binbin Tong ,  Liping Lei ,  Jianbo Xian

IPC: G02F1/1368 ,  G02F1/1362 ,  H01L27/12

Abstract: Provided is a substrate. The substrate includes a base substrate; and a plurality of sub-pixel structures arranged in an array on the base substrate, wherein the sub-pixel structure comprises: a thin film transistor disposed on the base substrate, the thin film transistor comprising a source and a drain; an insulating layer disposed on a side of the thin film transistor distal from the base substrate, a first via hole being formed in the insulating layer; a pixel electrode disposed on a side of the insulating layer distal from the base substrate, the pixel electrode being electrically connected to either the source or the drain through the first via hole; and a filling block disposed at the first via hole.

公开(公告)号：US20250164842A1

公开(公告)日：2025-05-22

申请号：US19028480

申请日：2025-01-17

Applicant: BOE Technology Group Co., Ltd.

Inventor： Binbin Tong ,  Lizhong Wang ,  Jianbo Xian ,  Liping Lei ,  Chunping Long ,  Yunping Di ,  Ce Ning

IPC: G02F1/1362 ,  G02F1/01 ,  G02F1/1333 ,  G02F1/1339 ,  G02F1/1343

Abstract: A display panel is disclosed. In the display panel, the second electrode is electrically connected to the first electrode through the first via hole, and a first support structure is provided in a region corresponding to the first via hole; and at least a part of the first support structure is located in the first via hole, and an orthographic projection of the first via hole on the base substrate at least partially overlaps with an orthographic projection of the gate line on the base substrate, the first support structure extends upward within the first via hole to an upper opening region of the first via hole, and a top of the first support structure is higher than the upper surface of the first interlayer insulating layer, a surface of the first support structure close to the second substrate is a curved surface.

公开(公告)号：US12276890B2

公开(公告)日：2025-04-15

申请号：US18005421

申请日：2022-03-30

Applicant: BOE Technology Group Co., Ltd.

Inventor： Binbin Tong ,  Lizhong Wang ,  Jianbo Xian ,  Liping Lei ,  Chunping Long ,  Yunping Di ,  Ce Ning

IPC: G02F1/1362 ,  G02F1/01 ,  G02F1/1333 ,  G02F1/1339 ,  G02F1/1343

Abstract: At least one embodiment of the present disclosure provides a display panel, and the display panel includes: a first substrate and a second substrate oppositely combined with each other, the first substrate includes a base substrate, and a gate line, a first electrode, a first interlayer insulating layer, and second electrode on the base substrate; the first interlayer insulating layer includes a first via hole penetrating through the first interlayer insulating layer, the second electrode is electrically connected to the first electrode the first via hole, first support structure is provided in a region corresponding to the first via hole and on a side of the second electrode away from the base substrate; at least a part of the first support structure is located in the first via hole, an orthographic projection of the first via hole overlaps with an orthographic projection of the gate line on the base substrate.

公开(公告)号：US20240103328A1

公开(公告)日：2024-03-28

申请号：US17765769

申请日：2021-06-29

Applicant: BOE Technology Group Co., Ltd.

Inventor： Zhen Zhang ,  Fuqiang Li ,  Zhenyu Zhang ,  Yunping Di ,  Lizhong Wang ,  Zheng Fang ,  Jiahui Han ,  Yawei Wang ,  Chenyang Zhang ,  Chengfu Xu ,  Ce Ning ,  Pengxia Liang ,  Feihu Zhou ,  Xianqin Meng ,  Weiting Peng ,  Qiuli Wang ,  Binbin Tong ,  Rui Huang ,  Tianmin Zhou ,  Wei Yang

IPC: G02F1/1368 ,  G02F1/1362 ,  H01L27/12

CPC classification number: G02F1/1368 ,  G02F1/136286 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1259

Abstract: A displaying base plate and a manufacturing method thereof, and a displaying device. The displaying base plate includes a substrate, and a first electrode layer disposed on one side of the substrate, wherein the first electrode layer includes a first electrode pattern; a first planarization layer disposed on one side of the first electrode layer that is away from the substrate, wherein the first planarization layer is provided with a through hole, and the through hole penetrates the first planarization layer, to expose the first electrode pattern; and a second electrode layer, a second planarization layer and a third electrode layer that are disposed in stack on one side of the first planarization layer that is away from the substrate, wherein the second electrode layer is disposed closer to the substrate, the second electrode layer is connected to the first electrode pattern and the third electrode layer.

公开(公告)号：US12235557B2

公开(公告)日：2025-02-25

申请号：US17765769

申请日：2021-06-29

Applicant: BOE Technology Group Co., Ltd.

Inventor： Zhen Zhang ,  Fuqiang Li ,  Zhenyu Zhang ,  Yunping Di ,  Lizhong Wang ,  Zheng Fang ,  Jiahui Han ,  Yawei Wang ,  Chenyang Zhang ,  Chengfu Xu ,  Ce Ning ,  Pengxia Liang ,  Feihu Zhou ,  Xianqin Meng ,  Weiting Peng ,  Qiuli Wang ,  Binbin Tong ,  Rui Huang ,  Tianmin Zhou ,  Wei Yang

IPC: G02F1/1368 ,  G02F1/1362 ,  H01L27/12

Abstract: A displaying base plate and a manufacturing method thereof, and a displaying device. The displaying base plate includes a substrate, and a first electrode layer disposed on one side of the substrate, wherein the first electrode layer includes a first electrode pattern; a first planarization layer disposed on one side of the first electrode layer that is away from the substrate, wherein the first planarization layer is provided with a through hole, and the through hole penetrates the first planarization layer, to expose the first electrode pattern; and a second electrode layer, a second planarization layer and a third electrode layer that are disposed in stack on one side of the first planarization layer that is away from the substrate, wherein the second electrode layer is disposed closer to the substrate, the second electrode layer is connected to the first electrode pattern and the third electrode layer.

公开(公告)号：US20240272497A1

公开(公告)日：2024-08-15

申请号：US18005421

申请日：2022-03-30

Applicant: BOE Technology Group Co., Ltd.

Inventor： Binbin Tong ,  Lizhong Wang ,  Jianbo Xian ,  Liping Lei ,  Chunping Long ,  Yunping Di ,  Ce Ning

IPC: G02F1/1362 ,  G02F1/1333 ,  G02F1/1343

CPC classification number: G02F1/136286 ,  G02F1/133308 ,  G02F1/13439

Abstract: At least one embodiment of the present disclosure provides a display panel, and the display panel includes: a first substrate and a second substrate oppositely combined with each other, the first substrate includes a base substrate, and a gate line, a first electrode, a first interlayer insulating layer, and second electrode on the base substrate; the first interlayer insulating layer includes a first via hole penetrating through the first interlayer insulating layer, the second electrode is electrically connected to the first electrode the first via hole, first support structure is provided in a region corresponding to the first via hole and on a side of the second electrode away from the base substrate; at least a part of the first support structure is located in the first via hole, an orthographic projection of the first via hole overlaps with an orthographic projection of the gate line on the base substrate.

公开(公告)号：US20240212564A1

公开(公告)日：2024-06-27

申请号：US17913258

申请日：2021-11-04

Applicant: BOE Technology Group Co., Ltd.

Inventor： Lizhong Wang ,  Ce Ning ,  Yunping Di ,  Binbin Tong ,  Chengfu Xu ,  Dapeng Xue ,  Shuilang Dong ,  Nianqi Yao

IPC: G09G3/20

CPC classification number: G09G3/2092 ,  G09G2300/0426 ,  G09G2300/0842 ,  G09G2310/0267 ,  G09G2310/062 ,  G09G2310/08

Abstract: A display substrate, a manufacturing method thereof and a display apparatus are provided. In the present disclosure, a first transistor group with oxide semiconductor as an active layer material is disposed on a side of a second transistor group with polysilicon as an active layer material away from the base, and an area enclosed by orthographic projections of the transistors in the first transistor group on the base is overlapped with an area enclosed by orthographic projections of the transistors in the second transistor group on the base. Stable performance of the transistors included can be ensured in a manufacturing process of the first transistor group and the second transistor group located in different layers, and at the same time, an area occupied by the driving circuit can be reduced so as to decrease a frame width of a display apparatus or improve resolution of the display apparatus.

公开(公告)号：US12217651B2

公开(公告)日：2025-02-04

申请号：US17913258

申请日：2021-11-04

Applicant: BOE Technology Group Co., Ltd.

Inventor： Lizhong Wang ,  Ce Ning ,  Yunping Di ,  Binbin Tong ,  Chengfu Xu ,  Dapeng Xue ,  Shuilang Dong ,  Nianqi Yao

IPC: G09G3/20

Abstract: A display substrate, a manufacturing method thereof and a display apparatus are provided. In the present disclosure, a first transistor group with oxide semiconductor as an active layer material is disposed on a side of a second transistor group with polysilicon as an active layer material away from the base, and an area enclosed by orthographic projections of the transistors in the first transistor group on the base is overlapped with an area enclosed by orthographic projections of the transistors in the second transistor group on the base. Stable performance of the transistors included can be ensured in a manufacturing process of the first transistor group and the second transistor group located in different layers, and at the same time, an area occupied by the driving circuit can be reduced so as to decrease a frame width of a display apparatus or improve resolution of the display apparatus.