公开(公告)号：US20090260228A1

公开(公告)日：2009-10-22

申请号：US12258060

申请日：2008-10-24

Applicant: Christian Val

Inventor： Christian Val

IPC: H05K3/36

CPC classification number: H01L22/32 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/481 ,  H01L24/19 ,  H01L24/96 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/6834 ,  H01L2221/68368 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/24137 ,  H01L2224/73267 ,  H01L2225/0652 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01061 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/18162 ,  H01L2924/351 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00

Abstract: The present invention relates to a process for the vertical interconnection of 3D electronic modules (100), a module comprising a stack of K electronic wafer levels (19) electrically connected together by conductors lying along the direction of the stack, which comprises steps consisting in: A) fabricating a batch of wafer levels (19) comprising n geometric features bounded by dicing lines (14), each feature being provided with at least one electronic component (6) surrounded by insulating resin (9) and connected to electrical connection pads (4), the pads being connected to electrical connection tracks (12) deposited on a dielectric layer (11); each track (12) extends as far as an electrode (13) interconnecting the tracks and located on the dicing lines (14), and comprises a curved segment (12a) defining a zone (15a) that surrounds a location intended to form a via, B) stacking and assembling the K wafer levels (19) so as to superpose said zones (15a); C) drilling vias (15) in the resin (9) plumb with the locations of the vias, D) metallizing the wall of the vias (15) by electrolytic growth; and E) cutting the stack along the dicing lines (14), the width of the cuts being greater than that of the electrode (13), so as to obtain the 3D electronic modules (100).

Abstract translation: 本发明涉及一种用于3D电子模块（100）的垂直互连的方法，包括通过沿堆叠方向的导体电连接在一起的K个电子晶片级（19）的堆叠的模块，其包括以下步骤： ：A）制造一批包含由切割线（14）限定的n个几何特征的晶片级（19），每个特征设置有至少一个由绝缘树脂（9）包围的电子部件（6），并连接到电连接焊盘 （4），所述焊盘连接到沉积在电介质层（11）上的电连接轨道（12）; 每个轨道（12）延伸到互连轨道并且位于切割线（14）上的电极（13），并且包括限定围绕旨在形成通孔的位置的区域（15a）的弯曲段（12a） B）堆叠和组装所述K晶片级（19）以便叠加所述区域（15a）; C）在具有通孔的位置的树脂（9）铅垂中钻孔（15），D）通过电解生长金属化通孔（15）的壁; 以及E）沿着切割线（14）切割所述堆叠，所述切口的宽度大于所述电极（13）的宽度，以便获得所述3D电子模块（100）。

公开(公告)号：US20080170374A1

公开(公告)日：2008-07-17

申请号：US11910433

申请日：2006-04-03

Applicant: Christian Val

Inventor： Christian Val

IPC: H05K7/00

CPC classification number: H01L23/4985 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/5387 ,  H01L25/105 ,  H01L2225/1064 ,  H01L2225/107 ,  H01L2924/0002 ,  H01L2924/19041 ,  H05K1/116 ,  H05K1/189 ,  H05K3/3436 ,  H05K2201/09572 ,  H05K2201/09663 ,  H05K2203/041 ,  H05K2203/0455 ,  Y02P70/613 ,  H01L2924/00

Abstract: The invention relates to an electronic module (100) comprising a stack of n packages (10, 10a, 10b) of predetermined thickness E, which are provided on a lower surface with connection balls (12) of predetermined thickness eb, said connection balls being connected to a printed circuit (20, 20a, 20b) for interconnecting the package. The printed circuit is placed on the lower surface of the package level with the balls, is drilled with metallized holes (23), in which the balls (12) are located and to which they are connected, and has a thickness eci less than eb so as to obtain a module with a total thickness not exceeding n (E+10% eb).

Abstract translation: 本发明涉及一种电子模块（100），其包括具有预定厚度E的n个封装（10,10a，10b）的堆叠，其被设置在具有预定厚度E的连接球（12）的下表面上， b，所述连接球连接到印刷电路（20,20a，20b），用于互连所述封装。 印刷电路被放置在具有球的包装水平的下表面上，钻有金属孔（23），其中球（12）位于其中并且它们被连接，并且具有厚度e 以获得总厚度不超过n（E + 10％e B b）的模块。

公开(公告)号：US06809367B2

公开(公告)日：2004-10-26

申请号：US10149789

申请日：2002-06-17

Applicant: Christian Val

Inventor： Christian Val

IPC: H01L27108

CPC classification number: H01L25/50 ,  H01L23/5222 ,  H01L24/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01056 ,  H01L2924/01058 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3025 ,  H05K1/0218 ,  H05K1/0231 ,  H05K1/184 ,  H05K1/185 ,  H05K3/045 ,  H05K3/403 ,  H05K2201/0715 ,  H05K2201/09181 ,  H05K2201/09645 ,  H05K2201/10643 ,  Y10T29/49146 ,  Y10T29/49165 ,  H01L2924/00

Abstract: The invention relates to a device for interconnecting, in three dimensions, electronic components. In order to decrease the parasitic capacitances between the connections and shielding of the device, metallized grooves are cut in the block of stacked circuits, just clipping the connection to conductors of which are set back from the corresponding face of the block. The assembly is then encapsulated with resin and shielded by metallization. The invention is especially applicable to producing electronic systems in three dimensions with a small size.

Abstract translation: 本发明涉及一种用于在三维中互连电子部件的装置。 为了减小连接之间的寄生电容和器件的屏蔽，金属化的沟槽被切割在堆叠电路的块中，仅限制与导体相对应的块的相应面的连接。 然后将组件用树脂包封并通过金属化屏蔽。 本发明特别适用于制造具有小尺寸的三维电子系统。

公开(公告)号：US06716672B2

公开(公告)日：2004-04-06

申请号：US10182720

申请日：2002-08-09

Applicant: Christian Val

Inventor： Christian Val

IPC: H01L2144

CPC classification number: H01L25/50 ,  H01L25/105 ,  H01L2224/48091 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2225/1029 ,  H01L2225/1064 ,  H01L2924/0102 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A method of interconnection in three dimensions and to an electronic device obtained by the method. To increase the compactness of integrated circuit modules, the method stacks and adhesively bonds packages containing a chip connected to output leads by connection conductors inside each package, cuts through the packages near the chips to form a block, the conductors being flush with the faces of the block, and makes the connections on the faces of the block by metalizing and then etching the outlines of the connections. The method also applies to the matching of packages in the replacement of obsolete circuits.

Abstract translation: 一种三维互连的方法和通过该方法获得的电子装置。 为了提高集成电路模块的紧凑性，该方法通过每个封装内的连接导体将包含连接到输出引线的芯片的封装和粘合地结合在一起，切割靠近芯片的封装形成块，导体与 并且通过金属化来形成块的表面上的连接，然后蚀刻连接的轮廓。 该方法还适用于替换过时电路中的包的匹配。

公开(公告)号：US06307261B1

公开(公告)日：2001-10-23

申请号：US08182093

申请日：1994-01-25

Applicant: Christian Val ,  Yves Van Campenhout ,  Dominique Gilet

Inventor： Christian Val ,  Yves Van Campenhout ,  Dominique Gilet

IPC: H01L2304

CPC classification number: H01L23/5385 ,  H01L23/485 ,  H01L25/0652 ,  H01L2224/274 ,  H01L2224/45144 ,  H01L2924/01079 ,  H01L2924/09701 ,  H05K1/0298 ,  H05K1/182 ,  H01L2924/00

Abstract: The semiconductor device comprises at least one chip arranged on a support. The chip is coated with an electrically insulating and heat-stable material. This electrically insulating and heat-stable material is penetrated by electrical-connection leads connecting sites of the chip to metallized contacts, and leads are substantially perpendicular both to the said sites and to the said metallized contacts.

Abstract translation: 半导体器件包括布置在支撑体上的至少一个芯片。 该芯片涂有电绝缘和热稳定材料。 这种电绝缘和热稳定的材料被电连接引线穿过，将芯片的位置连接到金属化触点，并且引线基本上垂直于所述部位和所述金属化触点。

公开(公告)号：US5637536A

公开(公告)日：1997-06-10

申请号：US416704

申请日：1995-04-13

Applicant: Christian Val

Inventor： Christian Val

IPC: H01L25/18 ,  H01L25/065 ,  H01L25/07 ,  H01L21/60

CPC classification number: H01L25/0657 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2225/06517 ,  H01L2225/06551 ,  H01L2225/06575 ,  H01L2225/06579 ,  H01L2225/06582 ,  H01L2924/01046

Abstract: A method and component resulting from interconnecting wafers in three dimensions, where the wafers include chips and the chips include pads. Steps in the method include connecting leads to the pads; stacking the wafers; embedding the stack by a selectively removable material; treating faces of the stack in order to reveal the leads; forming connections on the faces of the stack for interconnecting the leads; and removing the selectively removable material.

Abstract translation: PCT No.PCT / FR94 / 00986 Sec。 371日期1995年04月13日 102（e）1995年4月13日PCT PCT 1994年8月5日PCT公布。 第WO95 / 05677号公报 日期1995年2月23日由三维互连晶片产生的方法和部件，其中晶片包括芯片，芯片包括焊盘。 该方法中的步骤包括将引线连接到焊盘; 堆叠晶片; 通过选择性可移除的材料嵌入堆叠; 处理堆叠的面以便显露引线; 在所述堆叠的表面上形成用于互连所述引线的连接; 并移除可选择性地移除的材料。

公开(公告)号：US5526230A

公开(公告)日：1996-06-11

申请号：US124805

申请日：1993-09-21

Applicant: Christian Val

Inventor： Christian Val

IPC: H01L23/52 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10 ,  H01L25/11 ,  H01L25/18 ,  H05K7/20

CPC classification number: H01L25/0657 ,  H01L25/105 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06589 ,  H01L2225/1029 ,  H01L2225/1064 ,  H01L2225/1094 ,  H01L2924/0002

Abstract: A device and method for interconnection packages in a stack. Each package encapsulates, for example a semiconductor chip containing an integrated circuit, which for example may be a memory. The packages (2) which have connecting pins (21) are mounted on support grid (4) which preferably act as a heat shunt, and are stacked and linked to each other with a resin coating (5). A stack (3) is cut out so that the pins on the packages and one edge of the grids are flush with faces (31, 32) of the stack (3). Connections between the packages themselves, and between the packages and stack connecting pads, are made on the faces of the stack. The connecting pads are where necessary fitted with connecting pins.

Abstract translation: 用于堆叠中的互连包的设备和方法。 每个封装封装例如包含集成电路的半导体芯片，其例如可以是存储器。 具有连接销（21）的包装（2）安装在优选用作热分流器的支撑格栅（4）上，并且用树脂涂层（5）彼此堆叠和连接。 切割堆叠（3），使得包装上的销和栅格的一个边缘与堆叠（3）的面（31,32）齐平。 封装本身之间以及封装和堆叠连接焊盘之间的连接是在堆叠的表面上制成的。 连接垫在必要时装有连接销。

公开(公告)号：US5323533A

公开(公告)日：1994-06-28

申请号：US949558

申请日：1992-11-10

Applicant: Christian Val

Inventor： Christian Val

IPC: H01L21/60 ,  H01L21/48 ,  H01L23/12 ,  H01L23/498 ,  H01L23/50 ,  H05K1/02 ,  H05K3/34 ,  H05K1/00

CPC classification number: H01L23/66 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/48 ,  H05K1/0243 ,  H01L2223/6611 ,  H01L2223/6622 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/8592 ,  H01L24/28 ,  H01L24/29 ,  H01L24/45 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01058 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/1579 ,  H01L2924/16152 ,  H01L2924/167 ,  H01L2924/1679 ,  H01L2924/19051 ,  H01L2924/20752 ,  H01L2924/3011 ,  H05K2201/09809 ,  H05K2201/10689 ,  H05K3/3421 ,  Y10T29/49123 ,  Y10T29/49144

Abstract: An object of the invention is the production of coaxial connections for the input/output links of the component and/or of the housing which encapsulates it.More precisely, the component placed in a package (B), is conventionally connected by wires to its package; the wires are next covered by a first insulating layer (21) then by a second conducting layer (24) in such a way that this second layer is linked to the earth pads (P.sub.E1) of the package. The layers (21, 24) thus form collectively-produced coaxial structures with the connection wires (F). A similar process is used for the input/output connections (P) of the package itself.

Abstract translation: PCT No.PCT / FR92 / 00241 Sec。 371日期：1992年11月10日 102（e）日期1992年11月10日PCT 1991年3月17日PCT公布。 出版物WO92 / 17905 日期为1992年10月15日。本发明的一个目的是生产用于封装该部件和/或壳体的输入/输出链路的同轴连接。 更准确地说，放置在包装（B）中的部件通常通过电线连接到其包装; 导线接下来被第一绝缘层（21）覆盖，然后由第二导电层（24）覆盖，使得该第二层连接到封装的接地焊盘（PE1）。 因此，层（21,24）与连接线（F）形成共同生产的同轴结构。 类似的过程用于包装本身的输入/输出连接（P）。

公开(公告)号：US4517356A

公开(公告)日：1985-05-14

申请号：US539914

申请日：1983-10-07

Applicant: Francois Lambert ,  Christian Val

Inventor： Francois Lambert ,  Christian Val

IPC: C08G59/00 ,  B29C35/00 ,  B29K63/00 ,  C08G59/18 ,  C08J3/24 ,  C08F6/00 ,  B29C25/00

CPC classification number: C08J3/247 ,  C08J2363/00

Abstract: A method of polymerizing a thermosetting resin such as an epoxy resin charged with silver particles in which shaped bodies of the resin are brought cold into contact with vapor of an organic liquid boiling at a temperature of above 100.degree. C. so that a condensate from this liquid forms on the bodies in temperature equilibrium so that the heat of vaporization is transferred upon such condensation rapidly to the bodies and the latter are polymerized rapidly under the constant temperature and pressure conditions.

Abstract translation: 聚合热固性树脂如负载有银颗粒的环氧树脂的方法，其中使树脂成型体冷却与在高于100℃的温度下沸腾的有机液体的蒸气接触，从而得到来自其的冷凝物 在温度平衡的物体上形成液体，使得蒸发的热量在这种冷凝下迅速转移到物体上，并且在恒定的温度和压力条件下快速聚合。