公开(公告)号：US20050194349A1

公开(公告)日：2005-09-08

申请号：US10906682

申请日：2005-03-02

Applicant: Dyi-Chung Hu ,  Chih-Kung Huang ,  Chien-Nan Wu

Inventor： Dyi-Chung Hu ,  Chih-Kung Huang ,  Chien-Nan Wu

IPC: H01B13/00 ,  H01L21/48 ,  H01L23/28 ,  H01L23/498 ,  H05K1/00 ,  H05K3/00 ,  H05K3/06 ,  H05K3/24 ,  H05K3/38 ,  H05K3/40

CPC classification number: H05K1/028 ,  H01L21/4846 ,  H01L23/4985 ,  H01L2924/0002 ,  H05K3/002 ,  H05K3/064 ,  H05K3/244 ,  H05K3/383 ,  H05K3/4092 ,  H05K2201/0133 ,  H05K2201/0166 ,  H05K2201/0394 ,  H05K2201/0397 ,  H05K2203/0574 ,  H01L2924/00

Abstract: A method of fabricating a film carrier is provided. The method comprises the steps of providing a film; forming a metallic layer on the film, patterning the metallic layer by etching to form a plurality of metallic leads; and, patterning the film by etching to form a plurality of openings so that processing time and manufacturing cost are reduced.

Abstract translation: 提供一种制造薄膜载体的方法。 该方法包括提供薄膜的步骤; 在所述膜上形成金属层，通过蚀刻图案化所述金属层以形成多个金属引线; 并且通过蚀刻来图案化膜以形成多个开口，从而减少了处理时间和制造成本。

公开(公告)号：US06406928B1

公开(公告)日：2002-06-18

申请号：US09691330

申请日：2000-10-18

Applicant: Tean-Sen Jen ,  Dyi-Chung Hu

Inventor： Tean-Sen Jen ,  Dyi-Chung Hu

IPC: H01L2100

CPC classification number: G02F1/1362 ,  G02F1/136209 ,  G02F1/1368 ,  G02F2001/136231

Abstract: A simplified BCE process for forming a thin film transistor matrix for a liquid crystal display is disclosed. By using a backside exposure technique, the masking step for patterning an etch stopper layer can be omitted. By forming a pixel electrode layer before a data metal layer, a remaining portion of the data metal layer surrounding the pixel electrode can function as a black matrix after properly patterning and etching the data metal layer. The in-situ black matrix exempts from an additional step of providing a black matrix and solves the problem in alignment.

Abstract translation: 公开了用于形成用于液晶显示器的薄膜晶体管矩阵的简化的BCE工艺。 通过使用背面曝光技术，可以省略用于图案化蚀刻停止层的掩模步骤。 通过在数据金属层之前形成像素电极层，在对数据金属层进行适当图案化和蚀刻之后，围绕像素电极的数据金属层的剩余部分可以用作黑色矩阵。 原位黑矩阵免除了提供黑矩阵的额外步骤，并解决了对准中的问题。

公开(公告)号：US6099786A

公开(公告)日：2000-08-08

申请号：US605953

申请日：1996-02-23

Applicant: Dyi-Chung Hu ,  Sheng-Heisn Lin ,  Tai-Kang Wu ,  Sywe N. Lee

Inventor： Dyi-Chung Hu ,  Sheng-Heisn Lin ,  Tai-Kang Wu ,  Sywe N. Lee

IPC: G02F1/1337 ,  G02F1/1339 ,  B29D11/00

CPC classification number: G02F1/1339 ,  G02F1/133711 ,  Y10T428/1005

Abstract: A method of making accurate alignment layers in a liquid crystal display (LCD) cell is provided so that the LCD seal band can be placed as close to the pixel as possible. This method is implemented by ablating the apolyimide film on the glass substrates of the LCD cell to remove the alignment film where the sealing material is to be dispersed later. Thus, the sealing band can butt against the liquid crystal mixture without any clearance. In so doing, the display area is increased, and the reliability of the seal is improved.

Abstract translation: 提供了一种在液晶显示器（LCD）单元中制作精确对准层的方法，使得LCD密封带可以尽可能靠近像素放置。 该方法通过在LCD单元的玻璃基板上烧蚀聚酰亚胺膜以去除密封材料稍后分散的取向膜来实现。 因此，密封带可以无间隙地对着液晶混合物。 这样做，显示区域增加，并且提高了密封的可靠性。

公开(公告)号：US5412997A

公开(公告)日：1995-05-09

申请号：US989603

申请日：1992-12-11

Applicant: Dyi-Chung Hu ,  Jen-Huang Jeng

Inventor： Dyi-Chung Hu ,  Jen-Huang Jeng

IPC: G01N3/00 ,  G01N19/04 ,  G01N3/08

CPC classification number: G01N19/04 ,  G01N2203/0296

Abstract: The present invention comprises a test system for non-destructively testing the attachment strength of a plurality of electric wires each connected to a corresponding input/output (I/O) port in an integrated circuit (IC) dice. The test system comprises a test bench for placing said integrated circuit dice thereon. The test system further comprises a force asserting means including a testing pin for asserting a controlled amount of pressing force along a predefined direction to each of the electric wires near said corresponding I/O ports on said IC dice. The test system also includes a control means including a testing arm connecting to the testing pin for controlling and positioning the testing pin to apply the controlled amount of force to each of the electric wires. The control means further includes a force measurement means for measuring the amount of force applied to each of the electric wires. The control means further comprising a positioning means which includes a plurality of stepping motors for adjusting the position of the testing arm. A test computer is connected to the control means to control the control means whereby the testing processes are performed in an automated manner.

Abstract translation: 本发明包括用于非破坏性地测试多个电线的连接强度的测试系统，每个电线连接到集成电路（IC）芯片中的对应的输入/输出（I / O）端口。 测试系统包括用于将所述集成电路晶片放置在其上的测试台。 该测试系统还包括一个力确定装置，该力确定装置包括测试销，该测试销用于将所控制的按预定方向的按压力量确定到所述IC芯片上所述相应I / O端口附近的每根电线。 测试系统还包括控制装置，该控制装置包括连接到测试销的测试臂，用于控制和定位测试销，以将控制的力施加到每个电线。 控制装置还包括用于测量施加到每根电线的力的量的力测量装置。 该控制装置还包括定位装置，该定位装置包括用于调节测试臂位置的多个步进马达。 测试计算机连接到控制装置以控制控制装置，由此以自动方式执行测试过程。

公开(公告)号：US12198993B2

公开(公告)日：2025-01-14

申请号：US17849713

申请日：2022-06-27

Applicant: Dyi-Chung Hu

Inventor： Dyi-Chung Hu

IPC: H01L23/13 ,  H01L21/56 ,  H01L23/00 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528

Abstract: A manufacturing method of a circuit carrier with a chip mounted thereon is provided. A fine redistribution structure is formed over a first temporary carrier. A first release layer is applied on the first temporary carrier. A plurality of conductive connectors is formed on the fine redistribution structure to form a first portion. The fine redistribution structure and the conductive connectors are transferred to a second temporary carrier. The second temporary carrier is provided with a second release layer. The first temporary carrier is removed after the conductive connectors inserted into the second release layer. A surface finishing process is performed on the fine conductive pattern distributed on the fine redistribution structure to form a surface finishing layer. The fine redistribution structure and the surface finishing layer formed thereon are adhered to a third temporary carrier through a third release layer. The first portion is disposed on a second portion.

公开(公告)号：US11984403B2

公开(公告)日：2024-05-14

申请号：US17024676

申请日：2020-09-17

Applicant: Dyi-Chung Hu

Inventor： Dyi-Chung Hu

IPC: H01L23/532 ,  B23K1/00 ,  H01L21/48 ,  H01L23/00 ,  H01L21/60

CPC classification number: H01L23/53242 ,  B23K1/00 ,  H01L21/4853 ,  H01L23/53228 ,  H01L24/14 ,  H01L2021/60135

Abstract: An integrated substrate structure includes a redistribution film, a circuit substrate, and a plurality of conductive features. The redistribution film includes a fine redistribution circuitry, a circuit substrate is disposed over the redistribution film and includes a core layer and a coarse redistribution circuitry disposed in and on the core layer. The circuit substrate is thicker and more rigid than the redistribution film, and a layout density of the fine redistribution circuitry is denser than that of the coarse redistribution circuitry. The conductive features are interposed between the circuit substrate and the redistribution film to be connected to the fine redistribution circuitry and the coarse redistribution circuitry. A redistribution structure and manufacturing methods are also provided.

公开(公告)号：US10818584B2

公开(公告)日：2020-10-27

申请号：US15811634

申请日：2017-11-13

Applicant: Dyi-Chung Hu

Inventor： Dyi-Chung Hu

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/683 ,  H05K3/46 ,  H01L23/00

Abstract: A package substrate including a redistribution structure and a core is provided. The redistribution structure has a first redistribution surface and a bonding pad disposed on the first redistribution surface. The core is disposed on the redistribution structure and has a first core surface facing towards the first redistribution surface of the redistribution structure. The core has a first core pad disposed on the first core surface and directly bonded to the bonding pad, and the first core pad is offset from the bonding pad. A package structure is also provided.

公开(公告)号：US10304786B2

公开(公告)日：2019-05-28

申请号：US16129800

申请日：2018-09-13

Applicant: Dyi-Chung Hu

Inventor： Dyi-Chung Hu

IPC: B32B7/02 ,  H01L23/00 ,  H01L21/683 ,  B32B7/12 ,  H01L23/498 ,  H01L21/48 ,  H05K3/46 ,  H05K3/00

Abstract: A composite carrier is disclosed for warpage management as a temporary carrier in semiconductor process. Warpage is reduced for a product, semi-product, or build-up layer processed on the temporary composite carrier which is peeled off the temporary carrier in a later step. The composite carrier comprises a top substrate and a bottom substrate, an adhesive layer is configured in between the top substrate and a bottom substrate. One of the embodiments discloses the top substrate of the composite carrier having a lower CTE and the bottom substrate of the composite carrier having a higher CTE.

公开(公告)号：US10236245B2

公开(公告)日：2019-03-19

申请号：US15078010

申请日：2016-03-23

Applicant: Dyi-Chung Hu

Inventor： Dyi-Chung Hu

IPC: H01L23/49 ,  H01L23/498 ,  H01L23/31 ,  H01L21/48 ,  H01L23/538 ,  H01L21/683

Abstract: A package substrate with embedded circuit is disclosed. The package substrate comprises a redistribution layer, the redistribution layer comprises a plurality of circuits, each circuit of the plurality of circuits runs with a top surface coplanar with a top surface of the dielectric material.

公开(公告)号：US10157836B2

公开(公告)日：2018-12-18

申请号：US15807583

申请日：2017-11-09

Applicant: Dyi-Chung Hu

Inventor： Dyi-Chung Hu

IPC: H01L21/44 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522

Abstract: A fabrication process including the following steps for making a metal via structure is disclosed. A substrate with at least a metal pad configured thereon is prepared. A first dielectric layer configured on a top surface of the substrate has a first opening exposing a top surface of the metal pad. A patterned first photoresist having a second opening aligned with the first opening is applied on a top surface of the first dielectric layer. A first metal evaporation is performed to form a first adhesive layer conformably distributed on a wall surface of the first opening and on a top surface of the exposed area of the metal pad. A second metal evaporation is performed to form a first metal block. The first photoresist is stripped. The first metal block is flattened to have a top surface coplanar with a top surface of the first dielectric layer.