公开(公告)号：US12199027B2

公开(公告)日：2025-01-14

申请号：US18809280

申请日：2024-08-19

Applicant: Dyi-Chung Hu

Inventor： Dyi-Chung Hu

IPC: H01L23/15 ,  B32B3/26 ,  B32B17/10 ,  B32B38/00 ,  H01L23/48 ,  H01L23/498 ,  H05K1/03 ,  H01L23/00 ,  H01L23/31

Abstract: A glass core substrate includes a first glass layer; a second glass layer disposed on the first glass layer; a third glass layer disposed on the second glass layer; a first bonding layer disposed between the first glass layer and the second glass layer; a second bonding layer disposed between the second glass layer and the third glass layer; and a conductive connector, passing through the first glass layer, the first bonding layer, the second glass layer, the second bonding layer, and the third glass layer, wherein the conductive connector is configured to provide a vertical conductive path penetrating through the first glass layer, the first bonding layer, the second glass layer, the second bonding layer, and the third glass layer. A manufacturing method of a glass core substrate is also provided.

公开(公告)号：US12176277B2

公开(公告)日：2024-12-24

申请号：US17676862

申请日：2022-02-22

Applicant: Dyi-Chung Hu

Inventor： Dyi-Chung Hu

IPC: H01L23/498 ,  H01L23/538 ,  H01L25/065

Abstract: A package substrate including a first redistribution structure, a first bonding layer, a core, a second bonding layer and a second redistribution structure in a sequential order is provided. The first redistribution structure has a first redistribution surface and a first bonding pad disposed on the first redistribution surface. The second redistribution structure has a second redistribution surface and a second bonding pad disposed on the second redistribution surface. The core has a first core pad disposed on a first core surface, and a second core pad disposed on a second core surface opposite to the first core surface. The first core pad is directly bonded to first bonding pad and offset from first bonding pad. The first bonding pad and the first core pad are embedded in the first bonding layer. The second core pad is contacting the second bonding pad through a conductive portion of the second bonding layer. A package structure is also provided.

公开(公告)号：US12148726B2

公开(公告)日：2024-11-19

申请号：US18587993

申请日：2024-02-27

Applicant: Dyi-Chung Hu

Inventor： Dyi-Chung Hu

IPC: H01L23/00 ,  H01L23/498 ,  H01L25/065

Abstract: A semiconductor substrate structure including a first group of circuit structure, a second group of circuit structure, and a first device is provided. The first group of circuit structure includes multiple first wiring layers and multiple first conductive connectors, and each of the first conductive connectors includes a conductive cap. The second group of circuit structure includes multiple second wiring layers and multiple second conductive connectors. The first group of circuit structure and the second group of circuit structure are electrically connected through bonding of the first conductive connectors and the second conductive connectors to form a multilayer redistribution structure. The first device is disposed on the first group of circuit structure and electrically connected to portion of the first conductive connectors or the first device is disposed on the second group of circuit structure and electrically connected to portion of the second conductive connectors. A semiconductor structure and manufacturing method thereof are also provided.

公开(公告)号：US11948899B2

公开(公告)日：2024-04-02

申请号：US17979793

申请日：2022-11-03

Applicant: Dyi-Chung Hu

Inventor： Dyi-Chung Hu

IPC: H01L23/00

CPC classification number: H01L24/02 ,  H01L2224/02311 ,  H01L2224/02331 ,  H01L2224/02373 ,  H01L2924/16251

Abstract: A semiconductor substrate structure including a first group of circuit structure and a second group of circuit structure is provided. The first group of circuit structure includes multiple first wiring layers and multiple first conductive connectors, and each of the first conductive connectors includes a conductive cap. The second group of circuit structure includes multiple second wiring layers and multiple second conductive connectors. The first group of circuit structure and the second group of circuit structure are electrically connected through bonding of the first conductive connectors and the second conductive connectors to form a multilayer redistribution structure. A manufacturing method of the semiconductor substrate structure is also provided.

公开(公告)号：US11876291B2

公开(公告)日：2024-01-16

申请号：US17980536

申请日：2022-11-03

Applicant: Dyi-Chung Hu

Inventor： Dyi-Chung Hu

IPC: H01Q1/22 ,  H01Q1/50

CPC classification number: H01Q1/50 ,  H01Q1/2283

Abstract: A millimeter wave antenna module package structure includes a first group of circuit structure, a second group of circuit structure, and a plurality of joints. The first group of circuit structure includes at least one first circuit layer and a plurality of first conductive connectors, and the at least one first circuit layer includes an antenna pattern. The second group of circuit structure includes a plurality of second circuit layers and a plurality of second conductive connectors. The joints are disposed between the first group of circuit structure and the second group of circuit structure. The joints are connected to the first conductive connectors and the second conductive connectors, such that the first group of circuit structure is electrically connected to the second group of circuit structure to form a multi-layer redistribution structure. A manufacturing method of the millimeter wave antenna module package structure is also provided.

公开(公告)号：US10964580B2

公开(公告)日：2021-03-30

申请号：US15374622

申请日：2016-12-09

Applicant: Dyi-Chung Hu

Inventor： Dyi-Chung Hu

IPC: B32B3/02 ,  B32B9/00 ,  H01L21/02 ,  H01L21/683 ,  B32B9/04 ,  B32B15/04 ,  B32B17/06 ,  B32B3/30 ,  B32B15/01 ,  B32B15/18 ,  B32B15/20 ,  G03F7/20 ,  H01L21/027 ,  H01L21/288

Abstract: At least one wafer is embedded in a carrier to eliminate or at least reduce edge effect. The wafer reconfiguration is designed to improve a quality not only for spin coating process but also for electric plating process. An edge bead is formed on top of the carrier instead of being formed on top of the wafer so that a full top surface of the wafer can be active to the fabrication of chips and therefore more chips are yielded for a single wafer. The backside of the wafer is not contaminated by the coating according to the present invention. Further, dummy circuits can be made on top of the carrier so that electric plating uniformity for full area of a wafer can be improved.

公开(公告)号：US10395946B2

公开(公告)日：2019-08-27

申请号：US16177446

申请日：2018-11-01

Applicant: Dyi-Chung Hu

Inventor： Dyi-Chung Hu

IPC: H01L23/49 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L23/538 ,  H01L23/31

Abstract: A method for manufacturing an electronic package includes: forming a middle patterned conductive layer having a first surface, a second surface opposite to the first surface, and a plurality of middle conductive pads; forming a first redistribution circuitry on the first surface, wherein the first redistribution circuitry includes a first patterned conductive layer having a plurality of first conductive elements, each first conductive element has a first conductive via and pad that form a T-shaped section, and each first conductive via connects the corresponding middle conductive pad and is tapering; and forming a second redistribution circuitry on the second surface, wherein the second redistribution circuitry includes a second patterned conductive layer having a plurality of second conductive elements, each second conductive element has a second conductive via and pad that form an inversed T-shaped section, and each second conductive via connects the corresponding middle conductive pad and is tapering.

公开(公告)号：US10304794B2

公开(公告)日：2019-05-28

申请号：US15694858

申请日：2017-09-04

Applicant: Dyi-Chung Hu

Inventor： Dyi-Chung Hu

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L21/78 ,  H01L23/28 ,  H05K1/11 ,  H01L21/683 ,  H01L23/31 ,  H01L21/56 ,  H01L25/065

Abstract: A manufacturing method of an integrated circuit package including the following step is provided. A bottom redistribution layer according to IC design rule is fabricated. A top redistribution layer according to PCB design rule and using the first top pads as a starting point is fabricated. The bottom redistribution layer has a plurality of first bottom pads, a plurality of first top pads, at least one dielectric layer and a plurality of vias. Sides and the top of the bottom redistribution layer have interfaces with a lowermost dielectric layer of the top redistribution layer, a bottom surface of the lowermost dielectric layer opposite to the plurality of first top pads is coplanar with a bottom surface of the at least one dielectric layer opposite to the plurality of first top pads and surfaces of the plurality of first bottom pads exposed by the at least one dielectric layer.

公开(公告)号：US10049995B2

公开(公告)日：2018-08-14

申请号：US15708142

申请日：2017-09-19

Applicant: Dyi-Chung Hu

Inventor： Dyi-Chung Hu

IPC: H01L21/44 ,  H01L23/00 ,  H01L25/065

Abstract: A bonding film has at least a left longitudinal branch, and a lower latitudinal branch; a first bonding area is configured in a first branch, and a second bonding area is configured in a second branch. A plurality of outer top metal pads and a plurality of inner top metal pads are exposed on a top surface within each bonding area. A central chip is configured in a central area of the bonding film and is electrically coupled to the inner top metal pad, and at least two peripheral chips are configured neighboring to the central chip and electrically coupled to the outer top metal pads. Each of the inner top metal pads is electrically coupled to a corresponding outer top metal pad through an embedded circuitry. The central chip communicates with the peripheral chips through the inner top metal pad, embedded circuitry, and outer top metal pad of the bonding film.

公开(公告)号：US10002852B1

公开(公告)日：2018-06-19

申请号：US15380716

申请日：2016-12-15

Applicant: Dyi-Chung Hu

Inventor： Dyi-Chung Hu

IPC: H01L21/02 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00

Abstract: A first integrated circuit (IC) package has a package substrate on bottom. The package substrate comprises a bottom redistribution circuitry configured according to printed circuit board (PCB) design rule and a top redistribution circuitry configured according to integrated circuit (IC) design rule. The first IC package has a plurality of top metal pads and a plurality of copper pillars configured on a top side according to IC design rule. A second IC package has a plurality of bottom metal pads configured according to IC design rule configured on a top side of the first IC package. The first IC package electrically couples to the second IC package through the plurality of copper pillars.