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    Cache with DMA and dirty bits
    41.
    发明授权
    Cache with DMA and dirty bits 有权
    缓存与DMA和脏位

    公开(公告)号：US06754781B2

    公开(公告)日：2004-06-22

    申请号：US09932643

    申请日：2001-08-17

    Applicant: Gerard Chauvel ,  Serge Lasserre

    Inventor： Gerard Chauvel ,  Serge Lasserre

    IPC: G06F1208

    CPC classification number: G06F9/30043 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/329 ,  G06F12/0292 ,  G06F12/0804 ,  G06F12/0879 ,  G06F12/0891 ,  G06F12/1027 ,  G06F12/1081 ,  G06F2201/81 ,  G06F2201/885 ,  G06F2212/1028 ,  Y02D10/13 ,  Y02D10/24

    Abstract: A digital system and method of operation is provided in which the digital system has at least one processor, with an associated multi-segment cache memory circuit (506(n). Validity circuitry (VI) is connected to the memory circuit and is operable to indicate if each segment of the plurality of segments holds valid data. Dirty bit circuitry (DI) is connected to the memory circuit for indicating if data within the cache is incoherent with a secondary back-up memory. DMA circuitry can transfer (1652) blocks of data/instructions (1660) between the cache and a secondary memory (1602). A transfer mode circuit (1681) controls how DMA operations are affected by the dirty bits. If the transfer mode circuit is in a first mode, a DMA operation transfers only segments (1661) indicated as dirty (1685). If the transfer mode circuit is in a second mode, a DMA operation transfers and entire block of data (1660) without regard to dirty indicators (1686). DMA transfers from the cache to secondary memory are thereby configured to be responsive to the dirty bits. A dirty bit mode circuit (1680) controls how DMA transfers affect the dirty bits. When the mode circuit is in a first mode, DMA transfers set the affected dirty bits to a clean state. When the dirty bit mode circuitry is in an alternate mode, DMA transfers set the affected dirty bits to a dirty state. A cache clean operation will thus copy data provided by a DMA transfer and indicated as dirty into backup secondary memory.

    Abstract translation: 提供了一种数字系统和操作方法，其中数字系统具有至少一个具有相关联的多段高速缓冲存储器电路（506（n））的处理器，有效电路（VI）连接到存储器电路，并且可操作以 指示多个段的每个段是否保存有效数据，脏位电路（DI）连接到存储器电路，用于指示高速缓存内的数据是否与辅助备份存储器不相干，DMA电路可以传输（1652）块 传输模式电路（1681）控制DMA操作如何受脏位的影响，如果传输模式电路处于第一模式，DMA操作（1660） 只传输指示为脏的段（1661）（1685），如果传输模式电路处于第二模式，则DMA操作传输和整个数据块（1660），而不考虑脏指示器（1686）。 到二级记忆 从而被配置为响应于脏位。 脏位模式电路（1680）控制DMA传输如何影响脏位。 当模式电路处于第一模式时，DMA将受影响的脏位设置为干净状态。 当脏位模式电路处于交替模式时，DMA传送将受影响的脏位设置为脏状态。 因此，高速缓存清理操作将复制由DMA传输提供的数据，并将其标记为脏到备用辅助存储器中。

    Cache operation based on range of addresses
    42.
    发明授权
    Cache operation based on range of addresses 有权
    基于地址范围的缓存操作

    公开(公告)号：US06728838B2

    公开(公告)日：2004-04-27

    申请号：US09932634

    申请日：2001-08-17

    Applicant: Gerard Chauvel ,  Serge Lasserre

    Inventor： Gerard Chauvel ,  Serge Lasserre

    IPC: G06F1212

    CPC classification number: G06F1/329 ,  G06F1/206 ,  G06F1/3203 ,  G06F9/30047 ,  G06F12/0292 ,  G06F12/0804 ,  G06F12/0879 ,  G06F12/0891 ,  G06F12/1027 ,  G06F12/1081 ,  G06F2201/81 ,  G06F2201/885 ,  G06F2212/1028 ,  Y02D10/13 ,  Y02D10/24

    Abstract: A digital system and method of operation is provided in which the digital system has at least one processor, with an associated multi-segment cache memory circuit (1806(n). Validity circuitry (VI) and dirty bit circuitry (DI) is connected to the memory circuit and is operable to indicate if each segment of the plurality of segments holds valid data. Block circuitry (700, 702) is connected to the set of valid bits and dirty bits and is operable to invalidate a selected range of lines in response to a directive from the first processor. The block circuitry has a start register (700) and an end register (702) each separately loadable by the processor. The block circuitry can invalidate either a single line or a block of lines in response to an operation command from the processor, depending on whether the end register is loaded or not. Likewise, the block circuitry can clean a single line or a block of lines in response to an operation command from the processor.

    Abstract translation: 提供了一种数字系统和操作方法，其中数字系统具有至少一个处理器，具有相关联的多段高速缓冲存储器电路（1806（n）），有效电路（VI）和脏位电路（DI）连接到 存储器电路并且可操作以指示多个段中的每个段是否保存有效数据。块电路（700,702）连接到该组有效位和脏位，并且可操作以使响应中的所选行范围无效 块电路具有开始寄存器（700）和结束寄存器（702），每个开关寄存器（700）和终端寄存器（702）都可以由处理器分别加载。块电路可以响应于第一处理器使单行或一组线路无效 来自处理器的操作命令，取决于结束寄存器是否被加载。同样地，块电路可以响应于来自处理器的操作命令来清除单行或一行线。

    Protocol processor for the execution of a collection of instructions in a reduced number of operations
    44.
    发明授权
    Protocol processor for the execution of a collection of instructions in a reduced number of operations 失效
    协议处理器，用于执行少量操作中的指令集合

    公开(公告)号：US6085308A

    公开(公告)日：2000-07-04

    申请号：US989387

    申请日：1997-12-12

    Applicant: Gerard Chauvel ,  Francis Aussedat ,  Pierre Calippe

    Inventor： Gerard Chauvel ,  Francis Aussedat ,  Pierre Calippe

    IPC: G06F9/308 ,  G06F9/38

    CPC classification number: G06F9/3879 ,  G06F9/30018 ,  G06F9/3877

    Abstract: Protocol processor intended to be associated with at least one main processor of a system with a view to the execution of tasks to which the main processor is not suited. The protocol processor comprises a program part (30) including an incrementation register (31), a program memory (33) connected to the incrementation register (31) in order to receive addresses thereof, a decoding part (35) intended to receive instructions from the program memory (33) of the program part (30) with a view to executing an instruction in two cycles, and a data part (36) for executing the instruction.

    Abstract translation: 旨在与系统的至少一个主处理器相关联的协议处理器，以便执行主处理器不适合的任务。 协议处理器包括一个包括递增寄存器（31）的程序部分（30），连接到增量寄存器（31）以便接收地址的程序存储器（33），用于接收来自 程序部分（30）的程序存储器（33），用于执行两个周期的指令，以及用于执行指令的数据部分（36）。

    Virtual crosspoint memory
    45.
    发明授权
    Virtual crosspoint memory 失效
    虚拟交叉点内存

    公开(公告)号：US5544104A

    公开(公告)日：1996-08-06

    申请号：US404409

    申请日：1995-03-14

    Applicant: Gerard Chauvel

    Inventor： Gerard Chauvel

    IPC: G06F15/16 ,  G06F15/167 ,  G11C7/00 ,  G11C8/00 ,  H04L12/56 ,  H04Q3/00 ,  H04Q11/04 ,  G11C13/00

    CPC classification number: H04L12/5601 ,  H04L49/106 ,  H04L49/108 ,  H04L49/1576 ,  H04Q11/0478 ,  H04L2012/5681

    Abstract: An interconnection-point memory which includes an array of N1 input buses (Rj) intended to be connected to a first plurality of N1 data-sender devices, an array of N2 output buses (Ck) intended to be connected to a second plurality of N2 data-receiver devices, and interconnection means (17) for connecting the array of input buses to the array of output buses. The interconnection means include on the one hand, a third plurality of N3 switching memories (FIFO m) used as first-in, first-out FIFO devices provided with a write port (Din) and with a read port (Dout), and on the other hand, first control means (S[j,m],24a,24b) for connecting in a virtual manner the input port of at least one switching memory to a specified input bus, and second control means (S[k,m],24a',24b') for connecting in a virtual manner at least one output bus to the read port of the said switching memory, so that the said specified switching memory constitutes a temporary interconnection point, independent of the input buses and output buses to be interconnected. This interconnection-point memory enables Application to the asynchronous transfer of data between senders and receivers.

    Abstract translation: 一种互连点存储器，其包括旨在连接到第一多个N1数据发送器设备的N1输入总线阵列（Rj），旨在连接到第二多个N2的N2输出总线（Ck）的阵列 数据接收设备和用于将输入总线阵列连接到输出总线阵列的互连装置（17）。 互连装置一方面包括第三多个N3切换存储器（FIFO m），其被用作设置有写入端口（Din）和读取端口（Dout）的先进先出FIFO设备，并且接通 另一方面，用于以虚拟方式将至少一个切换存储器的输入端口连接到指定的输入总线的第一控制装置（S [j，m]，24a，24b）和第二控制装置（S [k，m ]，24a'，24b'），用于以虚拟的方式将至少一个输出总线连接到所述切换存储器的读取端口，使得所述指定的开关存储器构成临时互连点，独立于输入总线和输出总线 互连。 该互连点存储器使应用程序能够在发送方和接收方之间异步传输数据。

    Device for the testing and checking of the operation of blocks within an integrated circuit
    47.
    发明授权
    Device for the testing and checking of the operation of blocks within an integrated circuit 失效
    用于测试和检查集成电路中块的操作的装置

    公开(公告)号：US4811344A

    公开(公告)日：1989-03-07

    申请号：US21112

    申请日：1987-03-03

    Applicant: Gerard Chauvel ,  Jean Ciroux

    Inventor： Gerard Chauvel ,  Jean Ciroux

    IPC: H01L21/66 ,  G01R31/28 ,  G01R31/317

    CPC classification number: G01R31/317

    Abstract: Device for the testing and checking of the operation of blocks within an integrated circuit, characterized in that it is formed from a set of shift registers and logic circuits associated with each block of the circuit to be tested, the set of registers including at least one test register (35), one status register (36) and one mask register (37), the status register (36) being connected to the outputs (ST0 to ST15) of the block to be tested while the test and mask registers (35,37) and the logic circuits (38,39) are connected to a central processing unit (1) of the integrated circuit of which the blocks form part, the central processing unit (1) being also connected to the said blocks (7,10) by a common interrupt line (.SIGMA.INT).

    Abstract translation: 用于测试和检查集成电路内的块的操作的装置，其特征在于，其由与要测试的电路的每个块相关联的一组移位寄存器和逻辑电路形成，所述寄存器组包括至少一个 测试寄存器（35），一个状态寄存器（36）和一个屏蔽寄存器（37），状态寄存器（36）连接到被测试块的输出（ST0到ST15），同时测试和屏蔽寄存器 ，37）和所述逻辑电路（38,39）连接到所述块组成部分的所述集成电路的中央处理单元（1），所述中央处理单元（1）也连接到所述块（7， 10）由公共中断线（SIGMA INT）。

    Device for the composition of color component signals from luminance and chrominance signals and video display device comprising the application thereof
    48.
    发明授权
    Device for the composition of color component signals from luminance and chrominance signals and video display device comprising the application thereof 失效
    用于组合来自亮度和色度信号的彩色分量信号的装置和包括其应用的视频显示装置

    公开(公告)号：US4791476A

    公开(公告)日：1988-12-13

    申请号：US887583

    申请日：1986-07-18

    Applicant: Gerard Chauvel

    Inventor： Gerard Chauvel

    IPC: G09G5/02 ,  H04N9/67 ,  H04N11/06

    CPC classification number: G09G5/02 ,  H04N9/67

    Abstract: A color signal is encoded into luminance and chrominance signals. Relationships between the luminance and chrominance signals, and the color components are computed. A color component signal is generated by matrixing these relationships. In addition, a signal processor may be used to combine other video images with the color component signal.

    Abstract translation: 彩色信号被编码为亮度和色度信号。 计算亮度和色度信号与颜色分量之间的关系。 通过将这些关系矩阵化来生成颜色分量信号。 此外，信号处理器可以用于将其他视频图像与颜色分量信号组合。

    Performing java interrupt with two program counters
    50.
    发明授权
    Performing java interrupt with two program counters 有权
    用两个程序计数器执行java中断

    公开(公告)号：US08516502B2

    公开(公告)日：2013-08-20

    申请号：US11741237

    申请日：2007-04-27

    Applicant: Gerard Chauvel ,  Gilbert Cabillic ,  Jean-Philippe Lesot

    Inventor： Gerard Chauvel ,  Gilbert Cabillic ,  Jean-Philippe Lesot

    IPC: G06F3/00 ,  G06F9/44 ,  G06F9/46 ,  G06F13/00 ,  G06F9/455 ,  G06F9/45

    CPC classification number: G06F9/4812

    Abstract: A method and system for performing a Java interrupt. At least some of the illustrative embodiments are methods comprising executing a thread having a context on a stack based on a first program counter, detecting an interrupt while executing the thread (wherein execution of the thread is temporarily suspended), and executing a method portion to handle the interrupt (wherein the method portion is executed on the stack based on the first program counter, and wherein the context during execution of the method portion is the same as during execution of the thread).

    Abstract translation: 一种用于执行Java中断的方法和系统。 至少一些说明性实施例是包括基于第一程序计数器执行在堆栈上具有上下文的线程的方法，在执行线程的同时检测中断（其中线程的执行被暂停），并且执行方法部分 处理中断（其中基于第一程序计数器在堆栈上执行方法部分，并且其中方法部分的执行期间的上下文与执行线程期间相同）。

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