公开(公告)号：US20240021534A1

公开(公告)日：2024-01-18

申请号：US18374596

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Shawna M. LIFF ,  Adel A. ELSHERBINI ,  Johanna M. SWAN

IPC: H01L23/538 ,  H01L25/065

CPC classification number: H01L23/5389 ,  H01L25/065

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a first die comprising a first face and a second face; and a second die, the second die comprising a first face and a second face, wherein the second die further comprises a plurality of first conductive contacts at the first face and a plurality of second conductive contacts at the second face, and the second die is between first-level interconnect contacts of the microelectronic assembly and the first die.

公开(公告)号：US20230100228A1

公开(公告)日：2023-03-30

申请号：US17485217

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Gerald PASDAST ,  Sathya Narasimman TIAGARAJ ,  Adel A. ELSHERBINI ,  Tanay KARNIK ,  Dileep KURIAN ,  Julien SEBOT

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48

Abstract: Embodiments disclosed herein include dies and die modules. In an embodiment, a die comprises a substrate with a first surface and a second surface opposite from the first surface. In an embodiment the substrate comprises a semiconductor material. In an embodiment, first bumps with a first pitch are on the first surface of the substrate. In an embodiment, a first layer surrounds the first bumps, where the first layer comprises a dielectric material. In an embodiment, second bumps with a second pitch are on the substrate. In an embodiment, the second pitch is greater than the first pitch. In an embodiment, a second layer surrounds the second bumps, where the second layer comprises a dielectric material.

公开(公告)号：US20230077750A1

公开(公告)日：2023-03-16

申请号：US17473162

申请日：2021-09-13

Applicant: Intel Corporation

Inventor： Tanay KARNIK ,  Dileep KURIAN ,  Bradley JACKSON ,  Srivatsa RANGACHAR SRINIVASA ,  Jainaveen SUNDARAM PRIYA ,  Adel A. ELSHERBINI

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31

Abstract: Embodiments disclosed herein include die modules. In an embodiment, a die module comprises a plurality of first dies, and a second die under the plurality of first dies. In an embodiment, the second die is coupled to individual ones of the plurality of first dies. In an embodiment, the second die comprises a plurality of mesh stops, and conductive routing to electrically couple the mesh stops together.

公开(公告)号：US20220102261A1

公开(公告)日：2022-03-31

申请号：US17544693

申请日：2021-12-07

Applicant: Intel Corporation

Inventor： Adel A. ELSHERBINI ,  Mathew J. MANUSHAROW ,  Krishna BHARATH ,  William J. LAMBERT ,  Robert L. SANKMAN ,  Aleksandar ALEKSOV ,  Brandon M. RAWLINGS ,  Feras EID ,  Javier SOTO GONZALEZ ,  Meizi JIAO ,  Suddhasattwa NAD ,  Telesphor KAMGAING

IPC: H01L23/498 ,  H01F17/00 ,  H01F27/40 ,  H01L49/02 ,  H01F27/28 ,  H01F41/04 ,  H01G4/33 ,  H01L21/48 ,  H01L23/66

Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, a transformer may be formed in the electrical package. The transformer may include a first conductive loop that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first conductive loop from a second conductive loop that is formed in the package. Additional embodiments of the invention include forming a capacitor formed in the electrical package. For example, the capacitor may include a first capacitor plate that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first capacitor plate form a second capacitor plate that is formed in the package. The thin dielectric spacer material in the transformer and capacitor allow for increased coupling factors and capacitance density in electrical components.

公开(公告)号：US20220084736A1

公开(公告)日：2022-03-17

申请号：US17020200

申请日：2020-09-14

Applicant: Intel Corporation

Inventor： Beomseok CHOI ,  Adel A. ELSHERBINI

IPC: H01F27/28 ,  H01F38/14 ,  H01F17/00 ,  H01F27/24 ,  H01F27/40

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, an electronic package comprises a package substrate and a first region in the package substrate. In an embodiment, the first region comprises first conductive routing. The electronic package may further comprise a second region in the package substrate. In an embodiment, the second region comprises second conductive routing. In an embodiment, the second conductive routing is embedded in a magnetic material.

公开(公告)号：US20200235449A1

公开(公告)日：2020-07-23

申请号：US16841072

申请日：2020-04-06

Applicant: Intel Corporation

Inventor： Adel A. ELSHERBINI ,  Mathew MANUSHAROW ,  Krishna BHARATH ,  Zhichao ZHANG ,  Yidnekachew S. MEKONNEN ,  Aleksandar ALEKSOV ,  Henning BRAUNISCH ,  Feras EID ,  Javier SOTO

IPC: H01P3/06 ,  H01P3/02 ,  H05K1/02 ,  H01P3/08

Abstract: Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.

公开(公告)号：US20200212012A1

公开(公告)日：2020-07-02

申请号：US16639085

申请日：2017-09-30

Applicant: Intel Corporation

Inventor： Preston T. MEYERS ,  Javier A. FALCON ,  Shawna M. LIFF ,  Joe R. SAUCEDO ,  Adel A. ELSHERBINI ,  Albert S. LOPEZ ,  Johanna M. SWAN

IPC: H01L25/065 ,  H01L25/00

Abstract: A device package has substrates disposed on top of one another to form a stack, and pads formed on at least one of the top surface and the bottom surface of each of the substrates. The device package has interconnects electrically coupling at least one of the top surface and the bottom surface of each substrate to at least one of the top surface and the bottom surface of another substrate. The device package has pillars disposed between at least one of the top surface and the bottom surface of one or more substrates to at least one of the top surface and the bottom surface of other substrates. The device package also has adhesive layers formed between at least one of the top surface and the bottom surface of one or more substrates to at least one of the top surface and the bottom surface of other substrates.

公开(公告)号：US20200065263A1

公开(公告)日：2020-02-27

申请号：US15746792

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Shawna LIFF ,  Adel A. ELSHERBINI ,  Telesphor KAMGAING ,  Sasha N. OSTER ,  Gaurav CHAWLA

IPC: G06F13/14 ,  G02B6/42 ,  H04M9/06 ,  H01P5/00 ,  H01Q13/10 ,  H04B1/40 ,  H04B7/00

Abstract: Microelectronic package communication is described using radio interfaces connected through wiring. One example includes a system board, an integrated circuit chip, and a package substrate mounted to the system board to carry the integrated circuit chip, the package substrate having conductive connectors to connect the integrated circuit chip to external components. A radio on the package substrate is coupled to the integrated circuit chip to modulate the data onto a carrier and to transmit the modulated data. A radio on the system board receives the transmitted modulated data and demodulates the received data, and a cable interface is coupled to the system board radio to couple the received demodulated data to a cable.

公开(公告)号：US20190333882A1

公开(公告)日：2019-10-31

申请号：US16312904

申请日：2016-07-01

Applicant: INTEL CORPORATION

Inventor： Telesphor KAMGAING ,  Adel A. ELSHERBINI ,  Sasha N. OSTER

IPC: H01L23/66 ,  H01L23/498 ,  H01L21/48

Abstract: In various embodiments, disclosed herein are systems and methods directed to the fabrication of a coreless semiconductor package (e.g., a millimeter (mm)-wave antenna package) having an asymmetric build-up layer count that can be fabricated on both sides of a temporary substrate (e.g., a core). The asymmetric build-up layer count can reduce the overall layer count in the fabrication of the semiconductor package and can therefore contribute to fabrication cost reduction. In further embodiments, the semiconductor package (e.g., a millimeter (mm)-wave antenna packages) can further comprise dummification elements disposed near one or more antenna layers. Further, the dummification elements disposed near one or more antenna layers can reduce image current and thereby increasing the antenna gain and efficiency.

公开(公告)号：US20190113545A1

公开(公告)日：2019-04-18

申请号：US16096968

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： Georgios C. DOGIAMIS ,  Adel A. ELSHERBINI ,  Shawna M. LIFF ,  Johanna M. SWAN ,  Jelena CULIC-VISKOTA ,  Thomas L. SOUNART ,  Feras EID ,  Sasha N. OSTER

IPC: G01R15/20 ,  H01L41/06 ,  H01L41/12

Abstract: Embodiments of the invention include a current sensing device for sensing current in an organic substrate. The current sensing device includes a released base structure that is positioned in proximity to a cavity of the organic substrate and a piezoelectric film stack that is positioned in proximity to the released base structure. The piezoelectric film stack includes a piezoelectric material in contact with first and second electrodes. A magnetic field is applied to the current sensing device and this causes movement of the released base structure and the piezoelectric stack which induces a voltage (potential difference) between the first and second electrodes.