公开(公告)号：US20220094256A1

公开(公告)日：2022-03-24

申请号：US17025745

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Kaladhar RADHAKRISHNAN ,  Beomseok CHOI ,  Michael HILL

IPC: H02M1/00 ,  H02M3/07

Abstract: Embodiments disclosed herein include two stage voltage regulators for electronic systems. In an embodiment, a voltage regulator comprises a switched capacitor voltage regulator (SCVR). In an embodiment, the SCVR receives a first voltage as an input and outputs a plurality of SCVR output voltages. In an embodiment, the voltage regulator further comprises a low-dropout (LDO) regulator. In an embodiment, the LDO regulator receives one or more of the plurality of SCVR output voltages as LDO input voltages, and where the LDO regulator outputs a second voltage.

公开(公告)号：US20220085143A1

公开(公告)日：2022-03-17

申请号：US17023249

申请日：2020-09-16

Applicant: Intel Corporation

Inventor： Beomseok CHOI ,  Huong DO ,  Sai VADLAMANI

IPC: H01L49/02 ,  H01F27/28 ,  H01F27/32 ,  H01F27/245 ,  H01L23/31

Abstract: Embodiments disclosed herein include magnetic structures and methods of forming such structures. In an embodiment, the magnetic structure includes an interconnect. In an embodiment, the interconnect comprises a core, where the core has a thickness and a length between a first end and a second end. In an embodiment, the core is conductive. In an embodiment, the interconnect further comprises a magnetic sheet surrounding the core. In an embodiment, the magnetic sheet comprises is a magnetic layer with a microstructure that comprises grains that are substantially aligned in a single direction.

公开(公告)号：US20250040231A1

公开(公告)日：2025-01-30

申请号：US18914863

申请日：2024-10-14

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Pratik KOIRALA ,  Nicole K. THOMAS ,  Paul B. FISCHER ,  Adel A. ELSHERBINI ,  Tushar TALUKDAR ,  Johanna M. SWAN ,  Wilfred GOMES ,  Robert S. CHAU ,  Beomseok CHOI

IPC: H01L27/06 ,  H01L21/765 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L23/64 ,  H01L25/00 ,  H01L25/065 ,  H01L27/092 ,  H01L29/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/778 ,  H01L29/786

Abstract: Gallium nitride (GaN) three-dimensional integrated circuit technology is described. In an example, an integrated circuit structure includes a layer including gallium and nitrogen, a plurality of gate structures over the layer including gallium and nitrogen, a source region on a first side of the plurality of gate structures, a drain region on a second side of the plurality of gate structures, the second side opposite the first side, and a drain field plate above the drain region wherein the drain field plate is coupled to the source region. In another example, a semiconductor package includes a package substrate. A first integrated circuit (IC) die is coupled to the package substrate. The first IC die includes a GaN device layer and a Si-based CMOS layer.

公开(公告)号：US20220085142A1

公开(公告)日：2022-03-17

申请号：US17020467

申请日：2020-09-14

Applicant: Intel Corporation

Inventor： Beomseok CHOI

IPC: H01L49/02 ,  G05F1/10 ,  H01F17/04 ,  H01L23/498 ,  H01L23/64 ,  H01F17/00

Abstract: Embodiments disclosed herein include modular transformers that comprise a plurality of interconnected transformer modules. In an embodiment a transformer module comprises a first core, where the first core is conductive, and a second core adjacent to the first core, where the second core is conductive. In an embodiment, the transformer module further comprises a magnetic layer around the first core and the second core. In an embodiment, a first via through the magnetic layer is connected to the first core, and a second via through the magnetic layer is connected to the first core. In an embodiment, a third via through the magnetic layer is connected to the second core, and a fourth via through the magnetic layer is connected to the second core.

公开(公告)号：US20220084736A1

公开(公告)日：2022-03-17

申请号：US17020200

申请日：2020-09-14

Applicant: Intel Corporation

Inventor： Beomseok CHOI ,  Adel A. ELSHERBINI

IPC: H01F27/28 ,  H01F38/14 ,  H01F17/00 ,  H01F27/24 ,  H01F27/40

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, an electronic package comprises a package substrate and a first region in the package substrate. In an embodiment, the first region comprises first conductive routing. The electronic package may further comprise a second region in the package substrate. In an embodiment, the second region comprises second conductive routing. In an embodiment, the second conductive routing is embedded in a magnetic material.

公开(公告)号：US20220102344A1

公开(公告)日：2022-03-31

申请号：US17033509

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Pratik KOIRALA ,  Nicole K. THOMAS ,  Paul B. FISCHER ,  Adel A. ELSHERBINI ,  Tushar TALUKDAR ,  Johanna M. SWAN ,  Wilfred GOMES ,  Robert S. CHAU ,  Beomseok CHOI

IPC: H01L27/092 ,  H01L29/40 ,  H01L27/06 ,  H01L29/20 ,  H01L29/06 ,  H01L23/538

Abstract: Gallium nitride (GaN) three-dimensional integrated circuit technology is described. In an example, an integrated circuit structure includes a layer including gallium and nitrogen, a plurality of gate structures over the layer including gallium and nitrogen, a source region on a first side of the plurality of gate structures, a drain region on a second side of the plurality of gate structures, the second side opposite the first side, and a drain field plate above the drain region wherein the drain field plate is coupled to the source region. In another example, a semiconductor package includes a package substrate. A first integrated circuit (IC) die is coupled to the package substrate. The first IC die includes a GaN device layer and a Si-based CMOS layer.

公开(公告)号：US20220102339A1

公开(公告)日：2022-03-31

申请号：US17033513

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Pratik KOIRALA ,  Nicole K. THOMAS ,  Paul B. FISCHER ,  Adel A. ELSHERBINI ,  Tushar TALUKDAR ,  Johanna M. SWAN ,  Wilfred GOMES ,  Robert S. CHAU ,  Beomseok CHOI

IPC: H01L27/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/778 ,  H01L21/765 ,  H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L23/48 ,  H01L23/498 ,  H01L23/64 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: Gallium nitride (GaN) three-dimensional integrated circuit technology is described. In an example, an integrated circuit structure includes a layer including gallium and nitrogen, a plurality of gate structures over the layer including gallium and nitrogen, a source region on a first side of the plurality of gate structures, a drain region on a second side of the plurality of gate structures, the second side opposite the first side, and a drain field plate above the drain region wherein the drain field plate is coupled to the source region. In another example, a semiconductor package includes a package substrate. A first integrated circuit (IC) die is coupled to the package substrate. The first IC die includes a GaN device layer and a Si-based CMOS layer.

公开(公告)号：US20220084740A1

公开(公告)日：2022-03-17

申请号：US17020214

申请日：2020-09-14

Applicant: Intel Corporation

Inventor： Beomseok CHOI ,  Adel A. ELSHERBINI

IPC: H01F27/28 ,  H01F27/10

Abstract: Embodiments disclosed herein include electronic packages and methods of forming electronic packages. In an embodiment, an electronic package comprises, a package substrate, and a magnetic block, where the magnetic block passes through the package substrate. In an embodiment, the electronic package further comprises a fluidic path from an inlet to the package substrate to an outlet of the package substrate. In an embodiment, the electronic package further comprises a conductive winding in the package substrate, where the conductive winding wraps around the magnetic block, and where the conductive winding is tubular and the fluidic path passes through the conductive winding.