公开(公告)号：US11941169B2

公开(公告)日：2024-03-26

申请号：US17683533

申请日：2022-03-01

Applicant: Intel Corporation

Inventor： Ingo Wald ,  Brent E. Insko ,  Prasoonkumar Surti ,  Adam T. Lake ,  Peter L. Doyle ,  Daniel Pohl

IPC: G06F3/01 ,  G02B27/00

CPC classification number: G06F3/013 ,  G02B27/0093 ,  G06F3/011

Abstract: One embodiment of a virtual reality apparatus comprises: a graphics processing engine comprising a plurality of graphics processing stages, the graphics processing engine to render a plurality of image frames for left and right displays of a head mounted display (HMD); and foveation control hardware logic to independently control two or more of the plurality of graphics processing stages based on feedback received from an eye tracking module of the HMD, the feedback indicating a foveated region selected based on a current or anticipated direction of a user's gaze, the foveation control hardware logic to cause the two or more of the graphics processing stages to process the foveated region differently than other regions of the image frames.

公开(公告)号：US11721059B2

公开(公告)日：2023-08-08

申请号：US17473770

申请日：2021-09-13

Applicant: INTEL CORPORATION

Inventor： Ingo Wald ,  Carsten Benthin ,  Sven Woop

IPC: G06T15/06 ,  G06T7/50 ,  G06T15/00 ,  G06T15/50 ,  G06T1/20

CPC classification number: G06T15/06 ,  G06T7/50 ,  G06T15/005 ,  G06T15/506 ,  G06T1/20 ,  G06T2210/21

Abstract: Apparatus and method for programmable ray tracing with hardware acceleration on a graphics processor. For example, one embodiment of a graphics processor comprises shader execution circuitry to execute a plurality of programmable ray tracing shaders. The shader execution circuitry includes a plurality of single instruction multiple data (SIMD) execution units. Sorting circuitry regroups data associated with one or more of the programmable ray tracing shaders to increase occupancy for SIMD operations performed by the SIMD execution units; and fixed-function intersection circuitry coupled to the shader execution circuitry detects intersections between rays and bounding volume hierarchies (BVHs) and/or objects contained therein and to provide results indicating the intersections to the sorting circuitry.

公开(公告)号：US20220351325A1

公开(公告)日：2022-11-03

申请号：US17749266

申请日：2022-05-20

Applicant: Intel Corporation

Inventor： Altug Koker ,  Ingo Wald ,  David Puffer ,  Subramaniam M. Maiyuran ,  Prasoonkumar Surti ,  Balaji Vembu ,  Guei-Yuan Lueh ,  Murali Ramadoss ,  Abhishek R. Appu ,  Joydeep Ray

IPC: G06T1/20 ,  G06F9/46 ,  G06F9/48 ,  G06F9/30 ,  G06F9/38

Abstract: One embodiment provides a parallel processor comprising a memory interface and a processing array coupled with the memory interface. The processing array is configured to address memory accessed via the memory interface via a virtual address mapping and includes circuitry to resolve a page fault for the virtual address mapping, wherein each of the multiple compute blocks is separately preemptable.

公开(公告)号：US11436785B2

公开(公告)日：2022-09-06

申请号：US17223395

申请日：2021-04-06

Applicant: Intel Corporation

Inventor： Ingo Wald ,  Gabor Liktor ,  Carsten Benthin ,  Carson Brownlee ,  Johannes Guenther ,  Jefferson D. Amstutz

IPC: G06T15/06 ,  G06T15/00 ,  G06T9/00 ,  G06T15/04 ,  G06T15/80 ,  G06T17/10

Abstract: An apparatus and method for compressing ray tracing data prior to transmission between nodes. For example, one embodiment of an apparatus comprises: a first node comprising a first ray tracing engine, the first node communicatively coupled to a second node comprising a second ray tracing engine; first compression circuitry coupled to the first ray tracing engine, the first compression circuitry to perform compression on ray tracing data of the first ray tracing engine to produce a first compressed stream of ray tracing data; and interface circuitry to transmit the first compressed stream of ray tracing data from the first node to the second node.

公开(公告)号：US11354769B2

公开(公告)日：2022-06-07

申请号：US16924895

申请日：2020-07-09

Applicant: Intel Corporation

Inventor： Altug Koker ,  Ingo Wald ,  David Puffer ,  Subramaniam M. Maiyuran ,  Prasoonkumar Surti ,  Balaji Vembu ,  Guei-Yuan Lueh ,  Murali Ramadoss ,  Abhishek R. Appu ,  Joydeep Ray

IPC: G06T1/20 ,  G06F9/46 ,  G06F9/48 ,  G06F9/30 ,  G06F9/38

Abstract: One embodiment provides for a parallel processor comprising a processing array within the parallel processor, the processing array including multiple compute blocks, each compute block including multiple processing clusters configured for parallel operation, wherein each of the multiple compute blocks is independently preemptable. In one embodiment a preemption hint can be generated for source code during compilation to enable a compute unit to determine an efficient point for preemption.

公开(公告)号：US11295409B2

公开(公告)日：2022-04-05

申请号：US17097246

申请日：2020-11-13

Applicant: INTEL CORPORATION

Inventor： Carsten Benthin ,  Sven Woop ,  Ingo Wald

IPC: G06T15/00 ,  G06T1/20 ,  G06F9/38 ,  G06T17/10 ,  G06T15/06

Abstract: Apparatus and method for compressing an acceleration data structure such as a bounding volume hierarchy (BVH). For example, one embodiment of a graphics processing apparatus comprises: one or more cores to execute graphics instructions including instructions to perform ray tracing operations; and compression circuitry to compress lowest level nodes of a hierarchical acceleration data structure comprising a plurality of hierarchically arranged nodes, each of the lowest level nodes comprising pointers to leaf data; the compression circuitry to quantize the lowest level nodes to generate quantized lowest level nodes and to store each quantized lowest level node and associated leaf data without the pointers to the leaf data.

公开(公告)号：US11257180B2

公开(公告)日：2022-02-22

申请号：US16929790

申请日：2020-07-15

Applicant: Intel Corporation

Inventor： Travis T. Schluessler ,  Abhishek R. Appu ,  Ankur N. Shah ,  Joydeep Ray ,  Altug Koker ,  Jacek Kwiatkowski ,  Ingo Wald ,  Jefferson Amstutz ,  Johannes Guenther ,  Gabor Liktor ,  Elmoustapha Ould-Ahmed-Vall

IPC: G06T1/20 ,  G09G5/36 ,  G06F3/147 ,  G06F9/50 ,  G06F3/14

Abstract: Systems, apparatuses, and methods may provide for technology to process graphical data, and to modify a runtime environment in a parallel computing platform for a graphic environment.

公开(公告)号：US11120608B2

公开(公告)日：2021-09-14

申请号：US16145162

申请日：2018-09-27

Applicant: Intel Corporation

Inventor： Ingo Wald ,  Carsten Benthin ,  Sven Woop

IPC: G06T15/06 ,  G06T7/50 ,  G06T15/00 ,  G06T15/50 ,  G06T1/20

Abstract: Apparatus and method for programmable ray tracing with hardware acceleration on a graphics processor. For example, one embodiment of a graphics processor comprises shader execution circuitry to execute a plurality of programmable ray tracing shaders. The shader execution circuitry includes a plurality of single instruction multiple data (SIMD) execution units. Sorting circuitry regroups data associated with one or more of the programmable ray tracing shaders to increase occupancy for SIMD operations performed by the SIMD execution units; and fixed-function intersection circuitry coupled to the shader execution circuitry detects intersections between rays and bounding volume hierarchies (BVHs) and/or objects contained therein and to provide results indicating the intersections to the sorting circuitry.

公开(公告)号：US11074741B2

公开(公告)日：2021-07-27

申请号：US16944004

申请日：2020-07-30

Applicant: Intel Corporation

Inventor： Ingo Wald

IPC: G06T15/06 ,  G06T1/20 ,  G06T15/00

Abstract: An apparatus and method are described for utilizing volume proxies. For example, one embodiment of an apparatus comprises: a volume subdivision module to subdivide a volume into a plurality of partitions, the apparatus to process a first of the partitions and to distribute data associated with each of the other partitions to each of a plurality of nodes; a proxy generation module to compute a first proxy for the first partition, the first proxy to be transmitted to the plurality of nodes; and a ray tracing engine to perform one or more traversal/intersection operations for a current ray or group of rays using the first proxy; if the ray or group of rays interacts with the first proxy, then the ray tracing engine to send the ray(s) to a second node associated with the first proxy or retrieves data related to the interaction from the second node.

公开(公告)号：US20210027416A1

公开(公告)日：2021-01-28

申请号：US16929790

申请日：2020-07-15

Applicant: Intel Corporation

Inventor： Travis T. Schluessler ,  Abhishek R. Appu ,  Ankur N. Shah ,  Joydeep Ray ,  Altug Koker ,  Jacek Kwiatkowski ,  Ingo Wald ,  Jefferson Amstutz ,  Johannes Guenther ,  Gabor Liktor ,  Elmoustapha Ould-Ahmed-Vall

IPC: G06T1/20 ,  G09G5/36 ,  G06F3/147 ,  G06F9/50

Abstract: Systems, apparatuses, and methods may provide for technology to process graphical data, and to modify a runtime environment in a parallel computing platform for a graphic environment.