公开(公告)号：US11632130B2

公开(公告)日：2023-04-18

申请号：US17681364

申请日：2022-02-25

Applicant: Intel Corporation

Inventor： Zuoguo Wu ,  Debendra Das Sharma ,  Md. Mohiuddin Mazumder ,  Subas Bastola ,  Kai Xiao

IPC: H03M13/11 ,  G06F13/38 ,  G06F13/36 ,  G06F13/40 ,  G06F13/42

Abstract: An identification is made that a link is to exit an active state, the link comprising a plurality of lanes. Parity information is maintained for the lanes based on data previously sent over the link, and an indication of the parity information is sent prior to the exit from the active state.

公开(公告)号：US11461959B2

公开(公告)日：2022-10-04

申请号：US16865587

申请日：2020-05-04

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Atsuo Kuwahara ,  Hugues Labbe ,  Sameer Kp ,  Jonathan Kennedy ,  Abhishek R. Appu ,  Jeffery S. Boles ,  Balaji Vembu ,  Michael Apodaca ,  Slawomir Grajewski ,  Gabor Liktor ,  David M. Cimini ,  Andrew T. Lauritzen ,  Travis T. Schluessler ,  Murali Ramadoss ,  Abhishek Venkatesh ,  Joydeep Ray ,  Kai Xiao ,  Ankur N. Shah ,  Altug Koker

IPC: G06T15/40 ,  G06T1/20 ,  G06T15/30 ,  G06T15/00 ,  G06T11/40 ,  G06T17/20

Abstract: The systems, apparatuses and methods may provide a way to adaptively process and aggressively cull geometry data. Systems, apparatuses and methods may provide for processing, by a positional only shading pipeline (POSH), geometry data including surface triangles for a digital representation of a scene. More particularly, systems, apparatuses and methods may provide a way to identify surface triangles in one or more exclusion zones and non-exclusion zones, and cull surface triangles in one or more exclusion zones.

公开(公告)号：US20220021139A1

公开(公告)日：2022-01-20

申请号：US17483913

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Xiang Li ,  Shaohua Li ,  Kai Xiao ,  Mo Liu ,  Jingbo Li

IPC: H01R12/57 ,  H01R12/72 ,  H01R12/73

Abstract: In one embodiment, a card edge connector includes a housing including a slot to receive a first circuit board. A first plurality of pins extend from within the slot through a bottom of the housing. Each of the first plurality of pins includes a first end to mate with a corresponding contact of the first circuit board and a second end to mate with a corresponding one of a first plurality of contacts of a second circuit board, the second end including a heel portion and a toe portion extending from the heel portion in a direction away from a centerline of the slot. A second plurality of pins extend from within the slot through the bottom of the housing. Each of the second plurality of pins includes a first end to mate with a corresponding contact of the first circuit board and a second end to mate with a corresponding one of a second plurality of contacts of the second circuit board, the second end comprising a heel portion and a toe portion extending from the heel portion in a direction toward the centerline of the slot. Other embodiments are described and claimed.

公开(公告)号：US11169194B2

公开(公告)日：2021-11-09

申请号：US16799152

申请日：2020-02-24

Applicant: Intel Corporation

Inventor： Xiaoning Ye ,  Kai Xiao

IPC: G01R27/28

Abstract: Technologies for verifying a de-embedder for interconnect measurement include a verification compute device. The verification compute device is to measure a first signal transmitted through a single device under test and measure a second signal transmitted through a duplicated set of devices under test. Each device under test in the duplicated set is substantially identical to the single device under test. Additionally, the verification compute device is to apply a de-embedder to the measured first signal to remove an effect of test fixtures on the measured first signal, apply the de-embedder to the measured second signal to remove the effect of the test fixtures on the measured second signal, concatenate the de-embedded first signal with itself to generate a concatenated de-embedded first signal, and compare the concatenated de-embedded first signal with the de-embedded second signal to determine whether the concatenated de-embedded first signal matches the de-embedded second signal.

公开(公告)号：US20210263742A1

公开(公告)日：2021-08-26

申请号：US17195132

申请日：2021-03-08

Applicant: Intel Corporation

Inventor： Altug Koker ,  Michael Apodaca ,  Kai Xiao ,  Chandrasekaran Sakthivel ,  Jeffery S. Boles ,  Adam T. Lake ,  Abhishek R. Appu

IPC: G06F9/30 ,  G06F9/50 ,  G06T15/00 ,  G09G5/36 ,  G06T1/20

Abstract: Systems, apparatuses and methods may provide for technology that activates a first context on a graphics processor and detects a context switch condition with respect to the first context. Additionally, a second context may be activated, in response to the context switch condition, on the graphics processor while the first context is active on the graphics processor. In one example, activating the second context includes adding a group identifier to a plurality of threads corresponding to the second context and launching the plurality of threads with the group identifier on the graphics processor.

公开(公告)号：US10965047B2

公开(公告)日：2021-03-30

申请号：US16431498

申请日：2019-06-04

Applicant: Intel Corporation

Inventor： Jong-Ru Guo ,  Yunhui Chu ,  Jun Liao ,  Kai Xiao ,  Jingbo Li ,  Yuanhong Zhao ,  Mo Liu ,  Beomtaek Lee ,  James A. McCall ,  Jaejin Lee ,  Xiaoning Ye ,  Zuoguo Wu ,  Xiang Li

IPC: H05K7/00 ,  H01R12/71 ,  H01R13/66 ,  H01R103/00

Abstract: Embodiments may relate to a connector. The connector may include a plurality of connector pins that are to communicatively couple an element of a printed circuit board (PCB) with an element of an electronic device when the element of the PCB and the element of the electronic device are coupled with the connector. The connector may also include an active circuit that is communicatively coupled with a pin of the plurality of pins. The active circuit may be configured to match an impedance of the element of the PCB with an impedance of the element of the electronic device. Other embodiments may be described or claimed.

公开(公告)号：US10942740B2

公开(公告)日：2021-03-09

申请号：US16794973

申请日：2020-02-19

Applicant: Intel Corporation

Inventor： Altug Koker ,  Michael Apodaca ,  Kai Xiao ,  Chandrasekaran Sakthivel ,  Jeffery S. Boles ,  Adam T. Lake ,  Abhishek R. Appu

IPC: G06F9/30 ,  G06F9/50 ,  G06T15/00 ,  G09G5/36 ,  G06T1/20

Abstract: Systems, apparatuses and methods may provide for technology that activates a first context on a graphics processor and detects a context switch condition with respect to the first context. Additionally, a second context may be activated, in response to the context switch condition, on the graphics processor while the first context is active on the graphics processor. In one example, activating the second context includes adding a group identifier to a plurality of threads corresponding to the second context and launching the plurality of threads with the group identifier on the graphics processor.

公开(公告)号：US20210035270A1

公开(公告)日：2021-02-04

申请号：US16929787

申请日：2020-07-15

Applicant: Intel Corporation

Inventor： Tomer Bar-On ,  Hugues Labbe ,  Adam T. Lake ,  Kai Xiao ,  Ankur N. Shah ,  Johannes Guenther ,  Abhishek R. Appu ,  Joydeep Ray ,  Deepak S. Vembar ,  ElMoustapha Ould-Ahmed-Vall

IPC: G06T5/00 ,  G06T15/50 ,  G06T15/00 ,  G06T1/20 ,  G06T9/00 ,  G06T11/40

Abstract: Systems, apparatuses and methods may provide for technology that identifies, at an image post-processor, unresolved surface data and identifies, at the image post-processor, control data associated with the unresolved surface data. Additionally, the technology may resolve, at the image post-processor, the unresolved surface data and the control data into a final image.

公开(公告)号：US10893299B2

公开(公告)日：2021-01-12

申请号：US16050391

申请日：2018-07-31

Applicant: Intel Corporation

Inventor： Jill Boyce ,  Scott Janus ,  Itay Kaufman ,  Archie Sharma ,  Stanley Baran ,  Michael Apodaca ,  Prasoonkumar Surti ,  Srikanth Potluri ,  Barnan Das ,  Hugues Labbe ,  Jong Dae Oh ,  Gokcen Cilingir ,  Maria Bortman ,  Tzach Ashkenazi ,  Jonathan Distler ,  Atul Divekar ,  Mayuresh M. Varerkar ,  Narayan Biswal ,  Nilesh V. Shah ,  Atsuo Kuwahara ,  Kai Xiao ,  Jason Tanner ,  Jeffrey Tripp

IPC: H04N19/90 ,  H04N21/218 ,  G06T7/557 ,  G06T19/00 ,  G06T1/20 ,  G06T7/90

Abstract: An apparatus to facilitate processing video bit stream data is disclosed. The apparatus includes one or more processors to encode surface normals data with point cloud geometry data included in the video bit stream data for reconstruction of objects within the video bit stream data based on the surface normals data and a memory communicatively coupled to the one or more processors.

公开(公告)号：US20200334896A1

公开(公告)日：2020-10-22

申请号：US16865587

申请日：2020-05-04

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Atsuo Kuwahara ,  Hugues Labbe ,  Sameer Kp ,  Jonathan Kennedy ,  Abhishek R. Appu ,  Jeffery S. Boles ,  Balaji Vembu ,  Michael Apodaca ,  Slawomir Grajewski ,  Gabor Liktor ,  David M. Cimini ,  Andrew T. Lauritzen ,  Travis T. Schluessler ,  Murali Ramadoss ,  Abhishek Venkatesh ,  Joydeep Ray ,  Kai Xiao ,  Ankur N. Shah ,  Altug Koker

IPC: G06T15/40 ,  G06T1/20 ,  G06T15/30 ,  G06T15/00 ,  G06T11/40 ,  G06T17/20

Abstract: The systems, apparatuses and methods may provide a way to adaptively process and aggressively cull geometry data. Systems, apparatuses and methods may provide for processing, by a positional only shading pipeline (POSH), geometry data including surface triangles for a digital representation of a scene. More particularly, systems, apparatuses and methods may provide a way to identify surface triangles in one or more exclusion zones and non-exclusion zones, and cull surface triangles surface triangles in one or more exclusion zones.