中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

89 records (took 0.021 seconds)

    ANOMALY DETECTION IN A CONTROLLER AREA NETWORK
    41.
    发明申请
    ANOMALY DETECTION IN A CONTROLLER AREA NETWORK 审中-公开

    公开(公告)号：US20190044912A1

    公开(公告)日：2019-02-07

    申请号：US15942031

    申请日：2018-03-30

    Applicant: Intel Corporation

    Inventor： Liuyang Lily Yang ,  Huaxin Li ,  Li Zhao ,  Marcio Juliato ,  Shabbir Ahmed ,  Manoj R. Sastry

    IPC: H04L29/06 ,  G06F9/455

    Abstract: There is disclosed in one example a computing apparatus, including: a hardware platform; a network interface to communicatively couple to a bus lacking native support for authentication; and an anomaly detection engine to operate on the hardware platform and configured to: receive a first data stream across a first time; symbolize and approximate the first data stream, including computing a first window sum; receive a second data stream across a second time substantially equal in length to the first time, the second data stream including data across the plurality of dimensions from the first data stream; symbolize and approximate the second data stream, including computing a second window sum; compute a difference between the first window sum and the second window sum; determine that difference exceeds a threshold and that the correlation across the plurality of dimensions is broken; and flag a potential anomaly.

    Clock manager monitoring for time synchronized networks
    42.
    发明授权
    Clock manager monitoring for time synchronized networks 有权

    公开(公告)号：US12289161B2

    公开(公告)日：2025-04-29

    申请号：US17829042

    申请日：2022-05-31

    Applicant: INTEL CORPORATION

    Inventor： Vuk Lesi ,  Christopher Gutierrez ,  Manoj Sastry ,  Marcio Juliato ,  Shabbir Ahmed ,  Qian Wang

    IPC: H04J3/06

    Abstract: Techniques for clock manager monitoring for time sensitive networks are described. An apparatus, comprises a clock circuitry to manage a clock for a device, a processing circuitry coupled to the clock circuitry, the processing circuitry to execute instructions to perform operations for a clock manager, the clock manager to receive messages with time information for a network and generate clock manager control information to adjust the clock to a network time for the network, and a detector coupled to the processing circuitry and the clock circuitry, the detector to receive the clock manager control information, generate model control information based on a clock model, compare the clock manager control information with the model control information to generate difference information, and determine whether to generate an alert based on the difference information. Other embodiments are described and claimed.

    Security-Guided Adjustment of Time-Sync Frequency in Time Synchronized Networking
    48.
    发明公开
    Security-Guided Adjustment of Time-Sync Frequency in Time Synchronized Networking 审中-公开

    公开(公告)号：US20240171593A1

    公开(公告)日：2024-05-23

    申请号：US17990091

    申请日：2022-11-18

    Applicant: Intel Corporation

    Inventor： Marcio Juliato ,  Shabbir Ahmed ,  Christopher Gutierrez ,  Vuk Lesi ,  Manoj Sastry

    IPC: H04L9/40 ,  H04J3/06

    CPC classification number: H04L63/1416 ,  H04J3/0658 ,  H04L63/1466

    Abstract: Techniques include an apparatus to retrieve a first parameter for the IDS to monitor a device for a time-synchronized network. The first parameter may represent a number of messages the IDS needs to analyze in order to detect a security attack. The messages may comprise time information to synchronize a clock for a device to a network time for a time-synchronized network. The processor circuitry may retrieve a second parameter for a time sensitive application. The second parameter may represent a defined amount of time error tolerated by the time sensitive application, and determine a third parameter for the IDS based on the first and second parameters. The third parameter may represent a defined frequency to receive a number of messages with time information in order to detect the security attack on the device within a defined time interval. Other embodiments are described and claimed.

    CLOCK MANAGER REDUNDANCY FOR TIME SYNCHRONIZED NETWORKS
    49.
    发明公开
    CLOCK MANAGER REDUNDANCY FOR TIME SYNCHRONIZED NETWORKS 审中-公开

    公开(公告)号：US20240143020A1

    公开(公告)日：2024-05-02

    申请号：US17974113

    申请日：2022-10-26

    Applicant: Intel Corporation

    Inventor： Vuk Lesi ,  Christopher Gutierrez ,  Shabbir Ahmed ,  Marcio Juliato ,  Manoj Sastry

    IPC: G06F1/12 ,  G06F1/10

    CPC classification number: G06F1/12 ,  G06F1/10 ,  G06F1/08

    Abstract: An apparatus for clock manager redundancy comprises a clock circuitry to manage a clock for a device; a first processing circuitry coupled to the clock circuitry to execute instructions to perform operations for a clock manager, the clock manager to receive messages with time information for a network and generate clock manager control information to adjust the clock to a network time for the network; a hardened execution environment coupled to the clock circuitry and the first processing circuitry, the hardened execution environment to comprise: a detector to monitor the clock manager and generate an alert when the detector identifies abnormal behavior of the clock manager; and a second processing circuitry to execute instructions to perform operations for a redundant clock manager, the redundant clock manager to take over operations for the clock manager in response to the alert from the detector. Other embodiments are described and claimed.

Patent Agency Ranking