公开(公告)号：US10123431B2

公开(公告)日：2018-11-06

申请号：US15170444

申请日：2016-06-01

Applicant: Intel Corporation

Inventor： Yikang Deng

IPC: H05K3/42 ,  G01N21/95 ,  G01N21/64 ,  H05K1/02 ,  H05K3/00 ,  H05K1/11 ,  H05K1/09 ,  H05K3/46

Abstract: A microelectronic substrate may be fabricated having a substrate core with at least one plated through hole extending therethrough, wherein the plated through hole includes a fluorescent conductive fill material which can be utilized to detect defects during the fabrication process. In one embodiment, the microelectronic substrate may be fabricated by forming a substrate core, forming a hole to extend from a first surface to an opposing second surface of the substrate core, forming a conductive material layer on a sidewall(s) of the substrate core hole, disposing a fluorescent conductive fill material to abut the conductive material layer and fill the remaining substrate core hole, illuminating an exposed portion of the fluorescent conductive fill material, and detecting anomalies in the light fluoresced by the exposed portion of the fluorescent conductive fill material.

公开(公告)号：US20170221847A1

公开(公告)日：2017-08-03

申请号：US15485092

申请日：2017-04-11

Applicant: INTEL CORPORATION

Inventor： Yikang Deng

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L24/13 ,  H01L21/486 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49866 ,  H01L24/81 ,  H01L2224/13009 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13147 ,  H01L2224/13553 ,  H01L2224/1357 ,  H01L2224/81801 ,  H01L2924/014

Abstract: A microelectronic substrate may be formed to have an embedded trace which includes an integral attachment structure that extends beyond a first surface of a dielectric layer of the microelectronic substrate for the attachment of a microelectronic device. In one embodiment, the embedded trace may be fabricated by forming a dummy layer, forming a recess in the dummy layer, conformally depositing surface finish in the recess, forming an embedded trace layer on the dummy layer and abutting the surface finish, and removing the dummy layer.

公开(公告)号：US09653419B2

公开(公告)日：2017-05-16

申请号：US14681445

申请日：2015-04-08

Applicant: Intel Corporation

Inventor： Yikang Deng

IPC: H01L21/44 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L24/13 ,  H01L21/486 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49866 ,  H01L24/81 ,  H01L2224/13009 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13147 ,  H01L2224/13553 ,  H01L2224/1357 ,  H01L2224/81801 ,  H01L2924/014

Abstract: A microelectronic substrate may be formed to have an embedded trace which includes an integral attachment structure that extends beyond a first surface of a dielectric layer of the microelectronic substrate for the attachment of a microelectronic device. In one embodiment, the embedded trace may be fabricated by forming a dummy layer, forming a recess in the dummy layer, conformally depositing surface finish in the recess, forming an embedded trace layer on the dummy layer and abutting the surface finish, and removing the dummy layer.

公开(公告)号：US20160300807A1

公开(公告)日：2016-10-13

申请号：US14681445

申请日：2015-04-08

Applicant: Intel Corporation

Inventor： Yikang Deng

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L24/13 ,  H01L21/486 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49866 ,  H01L24/81 ,  H01L2224/13009 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13147 ,  H01L2224/13553 ,  H01L2224/1357 ,  H01L2224/81801 ,  H01L2924/014

Abstract: A microelectronic substrate may be formed to have an embedded trace which includes an integral attachment structure that extends beyond a first surface of a dielectric layer of the microelectronic substrate for the attachment of a microelectronic device. In one embodiment, the embedded trace may be fabricated by forming a dummy layer, forming a recess in the dummy layer, conformally depositing surface finish in the recess, forming an embedded trace layer on the dummy layer and abutting the surface finish, and removing the dummy layer.

Abstract translation: 微电子衬底可以形成为具有嵌入的迹线，其包括整体附接结构，其延伸超过微电子衬底的电介质层的第一表面，用于附接微电子器件。 在一个实施例中，嵌入迹线可以通过形成虚拟层，在虚设层中形成凹陷，在凹槽中共形沉积表面光洁度，在虚设层上形成嵌入的迹线层并邻接表面光洁度，并且去除 虚拟层。

公开(公告)号：US12288744B2

公开(公告)日：2025-04-29

申请号：US17742816

申请日：2022-05-12

Applicant: Intel Corporation

Inventor： Ji Yong Park ,  Kyu Oh Lee ,  Yikang Deng ,  Zhichao Zhang ,  Liwei Cheng ,  Andrew James Brown ,  Cheng Xu ,  Jiwei Sun

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a core substrate with a first conductive structure having a first thickness on the core substrate, and a second conductive structure having a second thickness on the core substrate, where the first thickness is different than the second thickness.

公开(公告)号：US11608564B2

公开(公告)日：2023-03-21

申请号：US17213622

申请日：2021-03-26

Applicant: Intel Corporation

Inventor： William J. Lambert ,  Mihir K Roy ,  Mathew J Manusharow ,  Yikang Deng

IPC: C25D7/00 ,  H01F17/00 ,  H01F41/04 ,  C25D5/16 ,  C25D5/48 ,  H01F27/255 ,  H01F27/28 ,  H01F41/02 ,  H01F27/24

Abstract: Devices and methods including a though-hole inductor for an electronic package are shown herein. Examples of the through-hole inductor include a substrate including at least one substrate layer. Each substrate layer including a dielectric layer having a first surface and a second surface. An aperture included in the dielectric layer is located from the first surface to the second surface. The aperture includes an aperture wall from the first surface to the second surface. A conductive layer is deposited on the first surface, second surface, and the aperture wall. At least one coil is cut from the conductive layer and located on the aperture wall.

公开(公告)号：US11521914B2

公开(公告)日：2022-12-06

申请号：US16233808

申请日：2018-12-27

Applicant: Intel Corporation

Inventor： Zhimin Wan ,  Cheng Xu ,  Yikang Deng ,  Junnan Zhao ,  Ying Wang ,  Chong Zhang ,  Kyu Oh Lee ,  Chandra Mohan Jha ,  Chia-Pin Chiu

IPC: H01L23/473 ,  H01L21/48

Abstract: Microelectronic assemblies that include a cooling channel, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a surface, a die having a surface, and a fluidic channel between the surface of the die and the surface of the package substrate, wherein a top surface of the fluidic channel is defined by the surface of the die and a bottom surface of the fluidic channel is defined by the surface of the package substrate. In some embodiments, a microelectronic assembly may include a package substrate having a surface; a die having a surface; and an interposer having a fluidic channel between the surface of the die and the surface of the package substrate.

公开(公告)号：US11246218B2

公开(公告)日：2022-02-08

申请号：US15910288

申请日：2018-03-02

Applicant: Intel Corporation

Inventor： Chong Zhang ,  Ying Wang ,  Junnan Zhao ,  Cheng Xu ,  Yikang Deng

IPC: H01L23/495 ,  H05K1/16 ,  H01L23/498 ,  H01L21/48 ,  H05K1/11 ,  H05K3/00 ,  H05K3/42 ,  H01F41/04 ,  H01F27/28 ,  H01F17/00 ,  H05K3/06 ,  H01L23/00

Abstract: Embodiments may include inductors with embedded magnetic cores and methods of making such inductors. In an embodiment, an integrated circuit package may include an integrated circuit die with a multi-phase voltage regulator electrically coupled to the integrated circuit die. In such embodiments, the multi-phase voltage regulator may include a substrate core and a plurality of inductors. The inductors may include a conductive through-hole disposed through the substrate core and a plugging layer comprising a dielectric material surrounding the conductive through-hole. In an embodiment, a magnetic sheath is formed around the plugging layer. In an embodiment, the magnetic sheath is separated from the plated through hole by the plugging layer. Additionally, a first layer comprising a dielectric material may be disposed over a first surface of the magnetic sheath, and a second layer comprising a dielectric material may be disposed over a second surface of the magnetic sheath.

公开(公告)号：US20200373257A1

公开(公告)日：2020-11-26

申请号：US16990782

申请日：2020-08-11

Applicant: Intel Corporation

Inventor： Cheng Xu ,  Yikang Deng ,  Kyu Oh Lee ,  Ji Yong Park ,  Srinivas Venkata Ramanuja Pietambaram ,  Ying Wang ,  Chong Zhang ,  Rui Zhang ,  Junnan Zhao

IPC: H01L23/64 ,  H01L23/522 ,  H01L23/528 ,  H01F27/24 ,  H01L27/04 ,  H01F27/28 ,  H01L21/822

Abstract: Techniques are provided for an inductor at a second level interface between a first substrate and a second substrate. In an example, the inductor can include a winding and a core disposed inside the winding. The winding can include first conductive traces of a first substrate, second conductive traces of a second non-semiconductor substrate, and a plurality of connectors configured to connect the first substrate with the second substrate. Each connector of the plurality of connectors can be located between a trace of the first conductive traces and a corresponding trace of the second conductive traces.

公开(公告)号：US10804188B2

公开(公告)日：2020-10-13

申请号：US16124838

申请日：2018-09-07

Applicant: Intel Corporation

Inventor： Yikang Deng ,  Ying Wang ,  Cheng Xu ,  Chong Zhang ,  Junnan Zhao

IPC: H01L23/498 ,  H01L23/538

Abstract: An electronic device may include a substrate, and the substrate may include one or more layers. The one or more layers may include a first dielectric material and one or more electrical traces. A cavity may be defined in the substrate, and the cavity may be adapted to receive one or more electrical components. One or more lateral traces may extend through a wall of the cavity. The lateral traces may provide electrical communication pathways between the substrate and the electrical components.