公开(公告)号：US10281975B2

公开(公告)日：2019-05-07

申请号：US15190417

申请日：2016-06-23

Applicant: Intel Corporation

Inventor： Efraim Rotem ,  Doron Rajwan ,  Eliezer Weissmann ,  Nir Rosenzweig ,  Eric Distefano ,  Ishmael F. Santos ,  James G. Hermerding, II

IPC: G06F1/00 ,  G06F1/26 ,  G06F1/32 ,  G06F1/3296 ,  G06F1/3228 ,  G06F9/30

Abstract: In one embodiment, a processor includes at least one core to execute instructions and a power controller coupled to the at least one core. The power controller may include a first logic to cause the at least one core to exit an idle state and enter into a maximum performance state for a first time duration, thereafter enter into an intermediate power state for a second time duration, and thereafter enter into a sustained performance state. Other embodiments are described and claimed.

公开(公告)号：US10268255B2

公开(公告)日：2019-04-23

申请号：US15197083

申请日：2016-06-29

Applicant: Intel Corporation

Inventor： Nir Rosenzweig ,  Efraim Rotem ,  Alexander Gendler ,  Ankush Varma

IPC: G06F1/26 ,  G06F1/28 ,  G06F9/38 ,  G06F9/44 ,  G06F1/32 ,  G06F1/324 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3203 ,  G06F1/3296 ,  G06F1/329

Abstract: A processor includes an execution engine and a power controller. The execution engine includes circuitry to determine an increased current for the execution engine. The power controller includes circuitry to determine a new dynamic capacitance for the execution engine based upon the increased current, calculate a new power consumption for the execution engine based upon the new dynamic capacitance, utilize the new power consumption to evaluate a new aggregate demand for power of a plurality of engines including the execution engine, and evaluate power provisioning of the processor based upon the new power consumption for the execution engine.

公开(公告)号：US20190102274A1

公开(公告)日：2019-04-04

申请号：US15720585

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Hisham Abu Salah ,  Arthur Leonard Brown ,  Russell J. Fenger ,  Deepak Samuel Kirubakaran ,  Asit K. Mallick ,  Jacob Jun Pan ,  Srinivas Pandruvada ,  Efraim Rotem ,  Arjan Van De Ven ,  Eliezer Weissmann ,  Rafal J. Wysocki

IPC: G06F11/34 ,  G06F9/48 ,  G06F9/50

Abstract: In an embodiment, a processor includes multiple processing engines and a power control unit. The power control unit is to: maintain a first utilization metric for a first processing engine; detect a thread transfer from a first processing engine to a second processing engine; and generate, using the first utilization metric for the first processing engine, a second utilization metric for a second processing engine. Other embodiments are described and claimed.

公开(公告)号：US10248181B2

公开(公告)日：2019-04-02

申请号：US15381241

申请日：2016-12-16

Applicant: Intel Corporation

Inventor： Avinash N. Ananthakrishnan ,  Inder M. Sodhi ,  Efraim Rotem ,  Doron Rajwan ,  Eliezer Weissmann ,  Ryan Wells

IPC: G06F1/32 ,  G06F1/324 ,  G06F1/3293 ,  G06F1/3203 ,  G11C7/22 ,  G06F13/42 ,  G06F1/3296 ,  G06F13/40

Abstract: In one embodiment, the present invention includes a processor having multiple domains including at least a core domain and a non-core domain that is transparent to an operating system (OS). The non-core domain can be controlled by a driver. In turn, the processor further includes a memory interconnect to interconnect the core domain and the non-core domain to a memory coupled to the processor. Still further, a power controller, which may be within the processor, can control a frequency of the memory interconnect based on memory boundedness of a workload being executed on the non-core domain. Other embodiments are described and claimed.

公开(公告)号：US10222851B2

公开(公告)日：2019-03-05

申请号：US15331051

申请日：2016-10-21

Applicant: Intel Corporation

Inventor： Efraim Rotem ,  Nir Rosenzweig ,  Doron Rajwan ,  Nadav Shulman ,  Gal Leibovich ,  Tomer Ziv ,  Amit Gabai ,  Jorge P. Rodriguez ,  Jeffrey A. Carlson

IPC: G06F1/32 ,  G06F1/324 ,  G05F1/10 ,  H03L7/08 ,  G06F1/28 ,  G06F1/3206

Abstract: A method and apparatus for providing proactive current protection. In one embodiment, the method comprises: prior to transitioning to a new state for an integrated circuit (IC), calculating a sum of expected powers for a plurality of domains in the IC by calculating an expected current for each of the plurality of domains based on an individual domain frequency in the new state and multiplying the expected current with its associated voltage for each of the plurality of domains for the new state; comparing the sum to a power limit; and if the sum is greater than the power limit, then reducing the individual domain frequency associated with at least one domain in the plurality of domains to maintain the total instantaneous power of the IC below the power limit.

公开(公告)号：US10175740B2

公开(公告)日：2019-01-08

申请号：US15135682

申请日：2016-04-22

Applicant: Intel Corporation

Inventor： Eliezer Weissmann ,  Efraim Rotem ,  Paul Diefenbaugh ,  Guy Therien ,  Nir Rosenzweig

IPC: G06F1/32

Abstract: In an embodiment, a processor includes multiple cores each to independently execute instructions and a power control unit (PCU) coupled to the plurality of cores to control power consumption of the processor. The PCU may include a mapping logic to receive a performance scale value from an operating system (OS) and to calculate a dynamic performance-frequency mapping based at least in part on the performance scale value. Other embodiments are described and claimed.

公开(公告)号：US10114448B2

公开(公告)日：2018-10-30

申请号：US14322185

申请日：2014-07-02

Applicant: Intel Corporation

Inventor： Jawad Haj-Yihia ,  Eliezer Weissmann ,  Vijay S R Degalahal ,  Nadav Shulman ,  Tal Kuzi ,  Itay Franko ,  Amit Gur ,  Efraim Rotem

IPC: G06F1/00 ,  G06F1/32

Abstract: Methods and apparatus relating to autonomous C state mechanism and computational engine alignment for improved processor power efficiency. are described. An embodiment determines whether a semiconductor package should enter a package C state based on energy consumption values for entry into and exit from the package C state, an amount of time the semiconductor package stayed in the package C state previously, and one or more breakeven time points between the various package C states. Another embodiment detects a delay by an imaging computational unit of a processor to enter a low power consumption state relative to one or more other computational units of the processor. The logic causes the imaging computational unit to enter the low power consumption state in response to detection of the delay. Other embodiments are also disclosed and claimed.

公开(公告)号：US10037067B2

公开(公告)日：2018-07-31

申请号：US15138505

申请日：2016-04-26

Applicant: Intel Corporation

Inventor： Avinash N. Ananthakrishnan ,  Inder M. Sodhi ,  Efraim Rotem ,  Doron Rajwan ,  Eliezer Weissmann ,  Ryan Wells

IPC: G06F1/26 ,  G06F1/32 ,  G11C7/22 ,  G06F13/42 ,  G06F13/40

CPC classification number: G06F1/324 ,  G06F1/3203 ,  G06F1/3293 ,  G06F1/3296 ,  G06F13/4068 ,  G06F13/4282 ,  G11C7/22 ,  Y02D10/122 ,  Y02D10/126 ,  Y02D10/151

Abstract: In one embodiment, the present invention includes a processor having multiple domains including at least a core domain and a non-core domain that is transparent to an operating system (OS). The non-core domain can be controlled by a driver. In turn, the processor further includes a memory interconnect to interconnect the core domain and the non-core domain to a memory coupled to the processor. Still further, a power controller, which may be within the processor, can control a frequency of the memory interconnect based on memory boundedness of a workload being executed on the non-core domain. Other embodiments are described and claimed.

公开(公告)号：US10013047B2

公开(公告)日：2018-07-03

申请号：US15143309

申请日：2016-04-29

Applicant: Intel Corporation

Inventor： Efraim Rotem ,  Oren Lamdan ,  Alon Naveh

IPC: G06F1/00 ,  G06F1/32 ,  G06F1/20 ,  G06F9/38 ,  G06F12/0862 ,  G06F12/0875 ,  G06F9/30

CPC classification number: G06F1/3287 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3275 ,  G06F1/3296 ,  G06F9/30083 ,  G06F9/3814 ,  G06F12/0862 ,  G06F12/0875 ,  G06F2212/452 ,  G06F2212/602 ,  Y02D10/126 ,  Y02D10/16 ,  Y02D10/172 ,  Y02D50/20

Abstract: For one disclosed embodiment, a processor comprises a plurality of processor cores to operate at variable performance levels. One of the plurality of processor cores may operate at one time at a performance level different than a performance level at which another one of the plurality of processor cores may operate at the one time. The plurality of processor cores are in a same package. Logic of the processor is to set one or more operating parameters for one or more of the plurality of processor cores. Logic of the processor is to monitor activity of one or more of the plurality of processor cores. Logic of the processor is to constrain power of one or more of the plurality of processor cores based at least in part on the monitored activity. The logic to constrain power is to limit a frequency at which one or more of the plurality of processor cores may be set. Other embodiments are also disclosed.

公开(公告)号：US20170364132A1

公开(公告)日：2017-12-21

申请号：US15182990

申请日：2016-06-15

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Efraim Rotem ,  Nir Rosenzweig ,  Krishnakanth V. Sistla ,  Ashish V. Choubal ,  Ankush Varma

IPC: G06F1/32

CPC classification number: G06F1/324 ,  G06F1/26 ,  G06F1/3206 ,  G06F1/3243 ,  G06F1/3287 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D10/172

Abstract: Apparatuses, methods and storage medium associated with current control for a multicore processor are disclosed herein. In embodiments, a multicore processor may include a plurality of analog current comparators, each analog current comparator to measure current utilization by a corresponding one of the cores of the multicore processor. The multicore processor may include one or more processors, devices, and/or circuitry to cause the cores to individually throttle based on measurements from the corresponding analog current comparators. In some embodiments, a memory device of the multicore processor may store instructions executable to operate a plurality power management agents to determine whether to send throttle requests based on a plurality of histories of the current measurements of the cores, respectively.