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公开(公告)号：US10083037B2
公开(公告)日：2018-09-25
申请号：US15281944
申请日：2016-09-30
Applicant: Intel Corporation
Inventor： Oren Ben-Kiki , Ilan Pardo , Robert Valentine , Eliezer Weissmann , Dror Markovich , Yuval Yosef
IPC: G06F9/38 , G06F9/30 , G06F11/07 , G06F9/54 , G06F12/0875
CPC classification number: G06F9/3802 , G06F9/3004 , G06F9/30043 , G06F9/30076 , G06F9/30101 , G06F9/30145 , G06F9/3016 , G06F9/384 , G06F9/3877 , G06F9/3879 , G06F9/3881 , G06F9/54 , G06F11/0721 , G06F11/0724 , G06F11/0772 , G06F12/0875 , G06F2212/452
Abstract: An apparatus and method are described for providing low-latency invocation of accelerators. For example, a processor according to one embodiment comprises: a plurality of simultaneous multithreading (SMT) cores, at least one shared cache circuit to be shared among the SMT cores, and at least one L2 cache circuit to store both instructions and data. The processor further comprises a communication interconnect circuit including a PCIe circuit to communicatively couple one or more of the SMT cores to an accelerator device, the PCIe circuit to provide the accelerator device access to resources of the processor including the at least one shared cache circuit. The processor further comprises a memory access circuit to identify an accelerator context save/restore region in a memory determined by an accelerator context save/restore value, the accelerator context save/restore region to store an accelerator context state.
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42.发明授权公开(公告)号：US09939879B2
公开(公告)日：2018-04-10
申请号：US14875930
申请日：2015-10-06
Applicant: Intel Corporation
Inventor： Avinash N. Ananthakrishnan , Efraim Rotem , Doron Rajwan , Jeremy J. Shrall , Eric C. Samson , Eliezer Weissmann , Ryan Wells
CPC classification number: G06F1/324 , G06F1/26 , G06F1/30 , G06F1/3203 , G06F1/3234 , G06F1/3243 , G06F13/14 , Y02D10/126
Abstract: In one embodiment, the present invention includes a method for determining that a non-core domain of a multi-domain processor is not operating at a frequency requested by the non-core domain, sending a request from the non-core domain to a power controller to reduce a frequency of a core domain of the multi-domain processor, and responsive to the request, reducing the core domain frequency. Other embodiments are described and claimed.
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公开(公告)号：US20180060078A1
公开(公告)日：2018-03-01
申请号：US15672254
申请日：2017-08-08
Applicant: Intel Corporation
Inventor： Eliezer Weissmann , Rinat Rappoport , Michael Mishaeli , Hisham Shafi , Oron Lenz , Jason W. Brandt , Stephen A. Fischer , Bret L. Toll , Inder M. Sodhi , Alon Naveh , Ganapati N. Srinivasa , Ashish V, Choubal , Scott D. Hahn , David A. Koufaty , Russel J. Fenger , Gaurav Khanna , Eugene Gorbatov , Mishali Naik , Andrew J. Herdrich , Abirami Prabhakaran , Sanjeev S. Sahagirdar , Paul Brett , Paolo Narvaez , Andrew D. Henroid , Dheeraj R. Subbareddy
Abstract: A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.
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公开(公告)号：US09811355B2
公开(公告)日：2017-11-07
申请号：US14338692
申请日：2014-07-23
Applicant: Intel Corporation
Inventor： Nir Rosenzweig , Efraim Rotem , Doron Rajwan , Nadav Shulman , Eliezer Weissmann
IPC: G06F1/32 , G06F9/445 , G06F12/0844 , G06F13/42
CPC classification number: G06F9/44505 , G06F1/324 , G06F12/0844 , G06F13/4234 , G06F2212/1052 , G06F2212/604 , Y02D10/14 , Y02D10/151
Abstract: In an embodiment, a processor includes at least one core and an interconnect that couples the at least one core and the cache memory. The interconnect is to operate at an interconnect frequency (fCL). The processor also includes a power management unit (PMU) including fCL logic to determine whether to adjust the fCL responsive to a Bayesian prediction value that is associated with scalability of a workload to be processed by the processor. The Bayesian prediction value may be determined based on one or more activity measures associated with the processor. Other embodiments are described and claimed.
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公开(公告)号：US09747221B2
公开(公告)日：2017-08-29
申请号：US14862745
申请日：2015-09-23
Applicant: Intel Corporation
Inventor： Gad Sheaffer , Boris Ginzburg , Ronny Ronen , Eliezer Weissmann
IPC: G06F12/1027 , G06F12/126 , G06F13/16 , G06F12/0804
CPC classification number: G06F12/1027 , G06F12/0804 , G06F12/126 , G06F13/1663 , G06F2212/303 , G06F2212/657 , G06F2212/684
Abstract: A computer system may support one or more techniques to allow dynamic pinning of the memory pages accessed by a non-CPU device, such as a graphics processing unit (GPU). The non-CPU may support virtual to physical address mapping and may thus be aware of the memory pages, which may not be pinned but may be accessed by the non-CPU. The non-CPU may notify or send such information to a run-time component such as a device driver associated with the CPU. The device driver may, dynamically, perform pinning of such memory pages, which may be accessed by the non-CPU. The device driver may even unpin the memory pages, which may be no longer accessed by the non-CPU. Such an approach may allow the memory pages, which may be no longer accessed by the non-CPU to be available for allocation to the other CPUs and/or non-CPUs.
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Patent Agency Ranking
公开(公告)号：US09671853B2
公开(公告)日：2017-06-06
申请号：US14484649
申请日：2014-09-12
Applicant: Intel Corporation
Inventor： Yoni Aizik , Eliezer Weissmann , Efraim Rotem , Yevgeni Sabin , Doron Rajwan , Ahmad Yasin
IPC: G06F1/32
CPC classification number: G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
Abstract: In an embodiment, a processor includes at least one core and energy performance gain (EPG) logic to determine an EPG frequency based on a first value of an EPG. The EPG is based upon energy consumed by the processor and upon performance of the processor. The processor also includes a clock generator to generate a frequency of operation of the at least one core based on the EPG frequency. Other embodiments are described and claimed.
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公开(公告)号：US20170097668A1
公开(公告)日：2017-04-06
申请号：US15381241
申请日：2016-12-16
Applicant: Intel Corporation
Inventor： Avinash N. Ananthakrishnan , Inder M. Sodhi , Efraim Rotem , Doron Rajwan , Eliezer Weissmann , Ryan Wells
CPC classification number: G06F1/324 , G06F1/3203 , G06F1/3293 , G06F1/3296 , G06F13/4068 , G06F13/4282 , G11C7/22 , Y02D10/122 , Y02D10/126 , Y02D10/151
Abstract: In one embodiment, the present invention includes a processor having multiple domains including at least a core domain and a non-core domain that is transparent to an operating system (OS). The non-core domain can be controlled by a driver. In turn, the processor further includes a memory interconnect to interconnect the core domain and the non-core domain to a memory coupled to the processor. Still further, a power controller, which may be within the processor, can control a frequency of the memory interconnect based on memory boundedness of a workload being executed on the non-core domain. Other embodiments are described and claimed.
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公开(公告)号：US20170083076A1
公开(公告)日：2017-03-23
申请号：US15367330
申请日：2016-12-02
Applicant: Intel Corporation
Inventor： Krishnakanth V. Sistla , Jeremy Shrall , Stephen H. Gunther , Efraim Rotem , Alon Naveh , Eliezer Weissmann , Anil Aggarwal , Martin T. Rowland , Ankush Varma , Ian M. Steiner , Matthew Bace , Avinash N. Ananthakrishnan , Jason Brandt
CPC classification number: G06F1/3275 , G06F1/266 , G06F1/3203 , G06F1/3206 , G06F1/3234
Abstract: In one embodiment, the present invention includes a processor having a core and a power controller to control power management features of the processor. The power controller can receive an energy performance bias (EPB) value from the core and access a power-performance tuning table based on the value. Using information from the table, at least one setting of a power management feature can be updated. Other embodiments are described and claimed.
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公开(公告)号：US09535487B2
公开(公告)日：2017-01-03
申请号：US14855553
申请日：2015-09-16
Applicant: Intel Corporation
Inventor： Krishnakanth V. Sistla , Jeremy Shrall , Stephen H. Gunther , Efraim Rotem , Alon Naveh , Eliezer Weissmann , Anil Aggarwal , Martin T. Rowland , Ankush Varma , Ian M. Steiner , Matthew Bace , Avinash N. Ananthakrishnan , Jason Brandt
CPC classification number: G06F1/3275 , G06F1/266 , G06F1/3203 , G06F1/3206 , G06F1/3234
Abstract: In one embodiment, the present invention includes a processor having a core and a power controller to control power management features of the processor. The power controller can receive an energy performance bias (EPB) value from the core and access a power-performance tuning table based on the value. Using information from the table, at least one setting of a power management feature can be updated. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，本发明包括具有核心的处理器和用于控制处理器的电源管理特征的功率控制器。 功率控制器可以从核心接收能量性能偏差（EPB）值，并根据该值访问功率性能调谐表。 使用表中的信息，可以更新电源管理功能的至少一个设置。 描述和要求保护其他实施例。
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公开(公告)号：US20160313778A1
公开(公告)日：2016-10-27
申请号：US15138505
申请日：2016-04-26
Applicant: Intel Corporation
Inventor： Avinash N. Ananthakrishnan , Inder M. Sodhi , Efraim Rotem , Doron Rajwan , Eliezer Weissmann , Ryan Wells
CPC classification number: G06F1/324 , G06F1/3203 , G06F1/3293 , G06F1/3296 , G06F13/4068 , G06F13/4282 , G11C7/22 , Y02D10/122 , Y02D10/126 , Y02D10/151
Abstract: In one embodiment, the present invention includes a processor having multiple domains including at least a core domain and a non-core domain that is transparent to an operating system (OS). The non-core domain can be controlled by a driver. In turn, the processor further includes a memory interconnect to interconnect the core domain and the non-core domain to a memory coupled to the processor. Still further, a power controller, which may be within the processor, can control a frequency of the memory interconnect based on memory boundedness of a workload being executed on the non-core domain. Other embodiments are described and claimed.
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