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41.发明申请公开(公告)号：US20150294648A1
公开(公告)日：2015-10-15
申请号：US14747682
申请日：2015-06-23
Applicant: Intel Corporation
Inventor： Eric C. Samson
CPC classification number: G09G5/18 , G06F1/324 , G09G5/363 , G09G2310/08 , G09G2330/021 , G09G2360/02 , G09G2360/12
Abstract: Systems and methods of adjusting a frequency of a graphics controller may include a logic to determine a metric associated with an input/output (I/O) queue. The metric may be used to determine whether an I/O limited condition exists. The I/O limited condition may be associated with a graphics controller. There may be a logic to cause a frequency of the graphics controller to be decreased when the I/O limited condition exists, and a logic to cause the frequency of the graphics controller to be increased when the I/O limited condition does not exist. The I/O limited condition may exist when a magnitude of the metric is equal to or greater than a first threshold. The I/O limited condition may not exist when the magnitude of the metric is equal to or less than a second threshold.
Abstract translation: 调整图形控制器的频率的系统和方法可以包括确定与输入/输出（I / O）队列相关联的度量的逻辑。 该度量可以用于确定是否存在I / O限制条件。 I / O限制条件可能与图形控制器相关联。 当存在I / O限制条件时，可能存在导致图形控制器的频率降低的逻辑，并且当I / O限制条件不存在时，导致图形控制器的频率增加的逻辑。 当度量的大小等于或大于第一阈值时，可能存在I / O限制条件。 当度量的大小等于或小于第二阈值时，I / O限制条件可能不存在。
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公开(公告)号：US09123088B2
公开(公告)日：2015-09-01
申请号：US13955228
申请日：2013-07-31
Applicant: Intel Corporation
Inventor： Nikos Kaburlasos , Eric C. Samson , Robert B. Taylor
CPC classification number: G06T1/20 , G06T1/00 , G06T1/60 , G09G5/001 , G09G5/363 , G09G5/395 , G09G2330/021 , G09G2360/08 , G09G2360/122 , G09G2360/18
Abstract: In accordance with some embodiments, partial rendering of non-changing or slowly changing frame tiles allows the graphics processing unit to spend less time processing non-changing or slowly changing portions of each frame, saving power and creating more room for performance in some embodiments.
Abstract translation: 根据一些实施例，不改变或缓慢变化的帧瓦片的部分渲染允许图形处理单元花费更少的时间处理每个帧的不变或缓慢变化的部分，从而在一些实施例中节省功率并创造更多的性能空间。
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公开(公告)号：US20210158471A1
公开(公告)日：2021-05-27
申请号：US17099118
申请日：2020-11-16
Applicant: Intel Corporation
Inventor： Murali Ramadoss , Balaji Vembu , Eric C. Samson , Kun Tian , David J. Cowperthwaite , Altug Koker , Zhi Wang , Joydeep Ray , Subramaniam M. Maiyuran , Abhishek R. Appu
Abstract: Embodiments described herein provide techniques enable a compute unit to continue processing operations when all dispatched threads are blocked. One embodiment provides for a method comprising executing multiple concurrent threads on a processing resource of a graphics processor, during execution, detecting that each of the multiple concurrent threads of the processing resource are blocked from execution, selecting a victim thread from the multiple concurrent threads, and suspending the victim thread. The thread state is stored to a thread scratch space in memory along with a blocking event associated with the victim thread.
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公开(公告)号：US10565676B2
公开(公告)日：2020-02-18
申请号：US15488547
申请日：2017-04-17
Applicant: Intel Corporation
Inventor： Adam T. Lake , Guei-Yuan Lueh , Balaji Vembu , Murali Ramadoss , Prasoonkumar Surti , Abhishek R. Appu , Altug Koker , Subramaniam M. Maiyuran , Eric C. Samson , David J. Cowperthwaite , Zhi Wang , Kun Tian , David Puffer , Brian T. Lewis
Abstract: An apparatus to facilitate data prefetching is disclosed. The apparatus includes a memory, one or more execution units (EUs) to execute a plurality of processing threads and prefetch logic to prefetch pages of data from the memory to assist in the execution of the plurality of processing threads.
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公开(公告)号：US10565079B2
公开(公告)日：2020-02-18
申请号：US15719541
申请日：2017-09-28
Applicant: Intel Corporation
Inventor： Eric C. Samson
IPC: G06F1/32 , G06F11/30 , G06F1/3287 , G06F1/3225 , G06F15/78 , G06F1/3234 , G06T1/20 , G06F12/084 , G06F12/0875 , G06F13/16 , G06F1/3203
Abstract: Methods and apparatus relating to techniques for determining idle power state are described. In an embodiment, power configuration logic determines a power state configuration for a portion of a processor. The power state configuration corresponds to a plurality of settings for operation of the portion of the processor during an idle period. Moreover, the power configuration logic determines the power state configuration based at least in part on one or more (e.g., runtime) workload measurements. Other embodiments are also disclosed and claimed.
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Patent Agency Ranking
公开(公告)号：US10560892B2
公开(公告)日：2020-02-11
申请号：US16243029
申请日：2019-01-08
Applicant: Intel Corporation
Inventor： Eric C. Samson , Murali Ramadoss , Marc Beuchat
Abstract: Methods and apparatus relating to advanced graphics Power State management are described. In one embodiment, measurement logic detects information about idle transitions and active transitions of a power-well of a processor. In turn, determination logic determines performance loss and/or energy gain based at least in part on the detected information and power-on latency of the power-well of the processor. Other embodiments are also disclosed and claimed.
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公开(公告)号：US20190095305A1
公开(公告)日：2019-03-28
申请号：US15719541
申请日：2017-09-28
Applicant: Intel Corporation
Inventor： Eric C. Samson
Abstract: Methods and apparatus relating to techniques for determining idle power state are described. In an embodiment, power configuration logic determines a power state configuration for a portion of a processor. The power state configuration corresponds to a plurality of settings for operation of the portion of the processor during an idle period. Moreover, the power configuration logic determines the power state configuration based at least in part on one or more (e.g., runtime) workload measurements. Other embodiments are also disclosed and claimed.
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公开(公告)号：US20180308209A1
公开(公告)日：2018-10-25
申请号：US16010692
申请日：2018-06-18
Applicant: Intel Corporation
Inventor： Murali Ramadoss , Balaji Vembu , Eric C. Samson , Kun Tian , David J. Cowperthwaite , Altug Koker , Zhi Wang , Joydeep Ray , Subramaniam M. Maiyuran , Abhishek R. Appu
Abstract: Embodiments described herein provide techniques enable a compute unit to continue processing operations when all dispatched threads are blocked. One embodiment provides for an apparatus comprising a thread dispatcher to dispatch a thread for execution; a compute unit having a single instruction, multiple thread architecture, the compute unit to execute multiple concurrent threads; and a memory coupled with the compute unit, the memory to store thread state for a suspended thread, wherein the compute unit is to: detect that all threads on the compute unit are blocked from execution, select a victim thread from the multiple concurrent threads, suspend the victim thread, store thread state of the victim thread to the memory, and replace the victim thread with an additional thread to be executed.
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公开(公告)号：US10043232B1
公开(公告)日：2018-08-07
申请号：US15482809
申请日：2017-04-09
Applicant: Intel Corporation
Inventor： Murali Ramadoss , Balaji Vembu , Eric C. Samson , Kun Tian , David J. Cowperthwaite , Altug Koker , Zhi Wang , Joydeep Ray , Subramaniam M. Maiyuran , Abhishek R. Appu
Abstract: One embodiment provides for a general-purpose graphics processing unit comprising a compute cluster including multiple compute units, a stall notification module to detect that one or more compute units in the compute cluster are stalled and send stall notification, and a rebalance module to receive the stall notification, the rebalance module to migrate a first workload from one or more stalled compute units in response to the stall notification.
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公开(公告)号：US09779694B2
公开(公告)日：2017-10-03
申请号：US14706410
申请日：2015-05-07
Applicant: Intel Corporation
Inventor： Murali Ramadoss , Eric C. Samson
CPC classification number: G06T1/20 , G06F1/324 , G06F1/3265 , G06F3/14 , G06T1/60 , G09G5/18 , G09G2330/021 , G09G2340/0435 , Y02D10/126 , Y02D10/153 , Y02D50/20
Abstract: Examples are disclosed for adjusting a performance state of a graphics subsystem and/or a processor based on a comparison of an average frame rate to a target frame rate and also based on whether the graphics subsystem is in a burst mode or sustained mode of operation.
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