公开(公告)号：US12020054B2

公开(公告)日：2024-06-25

申请号：US17256204

申请日：2018-11-30

Applicant: Intel Corporation

Inventor： Kun Tian ,  Ankur Shah ,  David Cowperthwaite ,  Zhi Wang ,  Zhenyu Wang ,  Kalyan Kondapally ,  Jonathan Bloomfield ,  Wei Zhang

IPC: G06F9/455 ,  G06F3/14 ,  G06F9/4401 ,  G06F9/451 ,  G09G5/00 ,  G09G5/393 ,  G09G5/395

CPC classification number: G06F9/45558 ,  G06F3/1407 ,  G06F9/4411 ,  G06F9/452 ,  G06F9/455 ,  G09G5/001 ,  G09G5/006 ,  G06F2009/45562 ,  G06F2009/45595 ,  G09G5/393 ,  G09G5/395

Abstract: Apparatus and method for implementing a virtual display. For example, one embodiment of a graphics processing apparatus comprises at least one configuration register to store framebuffer descriptor information for a first guest running on a first virtual machine (VM) in a virtualized execution environment of a host processor, the framebuffer descriptor information to indicate one or more display pipes assigned to the first guest; and execution circuitry to execute a first driver assigned to the first guest, the first guest to use the first driver to display a framebuffer in a plane associated with one of the display pipes in accordance with the framebuffer descriptor information.

公开(公告)号：US20220245752A1

公开(公告)日：2022-08-04

申请号：US17685445

申请日：2022-03-03

Applicant: Intel Corporation

Inventor： Murali Ramadoss ,  Balaji Vembu ,  Eric C. Samson ,  Kun Tian ,  David J. Cowperthwaite ,  Altug Koker ,  Zhi Wang ,  Joydeep Ray ,  Subramaniam M. Maiyuran ,  Abhishek R. Appu

IPC: G06T1/20 ,  G06F9/48 ,  G06F9/50 ,  G06F9/38

Abstract: Embodiments described herein provide techniques enable a graphics processor to continue processing operations during the reset of a compute unit that has experienced a hardware fault. Threads and associated context state for a faulted compute unit can be migrated to another compute unit of the graphics processor and the faulting compute unit can be reset while processing operations continue.

公开(公告)号：US20210216365A1

公开(公告)日：2021-07-15

申请号：US17058309

申请日：2018-09-19

Applicant: Intel Corporation

Inventor： Yan Zhao ,  Zhi Wang ,  Weinan Li

IPC: G06F9/48 ,  G06F9/50 ,  G06F9/30

Abstract: An embodiment of a semiconductor package apparatus may include technology to manage one or more virtual graphic processor units, and co-schedule the one or more virtual graphic processor units based on both general processor instructions and graphics processor instructions. Other embodiments are disclosed and claimed.

公开(公告)号：US09691123B2

公开(公告)日：2017-06-27

申请号：US14778508

申请日：2014-12-15

Applicant: Intel Corporation

Inventor： Zhi Wang ,  Yao Zu Dong

IPC: G06T1/20 ,  G06F7/00 ,  G06F11/36 ,  G06T1/60

CPC classification number: G06T1/20 ,  G06F7/00 ,  G06F11/3024 ,  G06F11/3419 ,  G06F11/3636 ,  G06F11/3644 ,  G06T1/60

Abstract: Embodiments of graphics instruction instrumentor (“GII”) and a graphics profiler (“GP”) are described. The GII may facilitate profiling of execution of graphics instructions by one or more graphics processors. The GII may identify target graphics instructions for which execution profile information is desired. The GII may store instrumentation graphics instructions in a graphics instruction buffer. The instrumentation graphics instructions may facilitate the GP in collecting graphics profile information. For example, timestamp-storage instructions may be store timestamps before and after execution of the target graphics instructions. The GII also may store an interrupt-generation instruction to cause an interrupt to be sent to the GP so that the GP may begin collection of graphics profile data. The GII may store an event-wait instruction to pause the graphics processors until an event is received. Other embodiments may be described and claimed.

公开(公告)号：US20210158471A1

公开(公告)日：2021-05-27

申请号：US17099118

申请日：2020-11-16

Applicant: Intel Corporation

Inventor： Murali Ramadoss ,  Balaji Vembu ,  Eric C. Samson ,  Kun Tian ,  David J. Cowperthwaite ,  Altug Koker ,  Zhi Wang ,  Joydeep Ray ,  Subramaniam M. Maiyuran ,  Abhishek R. Appu

IPC: G06T1/20 ,  G06F9/48 ,  G06F9/50 ,  G06F9/38

Abstract: Embodiments described herein provide techniques enable a compute unit to continue processing operations when all dispatched threads are blocked. One embodiment provides for a method comprising executing multiple concurrent threads on a processing resource of a graphics processor, during execution, detecting that each of the multiple concurrent threads of the processing resource are blocked from execution, selecting a victim thread from the multiple concurrent threads, and suspending the victim thread. The thread state is stored to a thread scratch space in memory along with a blocking event associated with the victim thread.

公开(公告)号：US10565676B2

公开(公告)日：2020-02-18

申请号：US15488547

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Adam T. Lake ,  Guei-Yuan Lueh ,  Balaji Vembu ,  Murali Ramadoss ,  Prasoonkumar Surti ,  Abhishek R. Appu ,  Altug Koker ,  Subramaniam M. Maiyuran ,  Eric C. Samson ,  David J. Cowperthwaite ,  Zhi Wang ,  Kun Tian ,  David Puffer ,  Brian T. Lewis

IPC: G06T1/20 ,  G06T1/60

Abstract: An apparatus to facilitate data prefetching is disclosed. The apparatus includes a memory, one or more execution units (EUs) to execute a plurality of processing threads and prefetch logic to prefetch pages of data from the memory to assist in the execution of the plurality of processing threads.

公开(公告)号：US20180308209A1

公开(公告)日：2018-10-25

申请号：US16010692

申请日：2018-06-18

Applicant: Intel Corporation

Inventor： Murali Ramadoss ,  Balaji Vembu ,  Eric C. Samson ,  Kun Tian ,  David J. Cowperthwaite ,  Altug Koker ,  Zhi Wang ,  Joydeep Ray ,  Subramaniam M. Maiyuran ,  Abhishek R. Appu

IPC: G06T1/20 ,  G06F9/48 ,  G06F9/50

Abstract: Embodiments described herein provide techniques enable a compute unit to continue processing operations when all dispatched threads are blocked. One embodiment provides for an apparatus comprising a thread dispatcher to dispatch a thread for execution; a compute unit having a single instruction, multiple thread architecture, the compute unit to execute multiple concurrent threads; and a memory coupled with the compute unit, the memory to store thread state for a suspended thread, wherein the compute unit is to: detect that all threads on the compute unit are blocked from execution, select a victim thread from the multiple concurrent threads, suspend the victim thread, store thread state of the victim thread to the memory, and replace the victim thread with an additional thread to be executed.

公开(公告)号：US10043232B1

公开(公告)日：2018-08-07

申请号：US15482809

申请日：2017-04-09

Applicant: Intel Corporation

Inventor： Murali Ramadoss ,  Balaji Vembu ,  Eric C. Samson ,  Kun Tian ,  David J. Cowperthwaite ,  Altug Koker ,  Zhi Wang ,  Joydeep Ray ,  Subramaniam M. Maiyuran ,  Abhishek R. Appu

IPC: G06F9/50 ,  G06F9/48 ,  G06T1/20

Abstract: One embodiment provides for a general-purpose graphics processing unit comprising a compute cluster including multiple compute units, a stall notification module to detect that one or more compute units in the compute cluster are stalled and send stall notification, and a rebalance module to receive the stall notification, the rebalance module to migrate a first workload from one or more stalled compute units in response to the stall notification.

公开(公告)号：US11886906B2

公开(公告)日：2024-01-30

申请号：US17343078

申请日：2021-06-09

Applicant: Intel Corporation

Inventor： Chuanxiao Dong ,  Yaozu Dong ,  Zhiyuan Lv ,  Zhi Wang

IPC: G06F9/455 ,  G06F9/48

CPC classification number: G06F9/45558 ,  G06F9/485 ,  G06F2009/45583 ,  G06F2009/45591

Abstract: Implementations disclosed describe a system and a method to execute a virtual machine on a processing device, receive a request to access a memory page identified by a guest virtual memory address (GVA) in an address space of the virtual machine, translate the GVA to a guest physical memory address (GPA) using a guest page table (GPT) comprising a GPT entry mapping the GVA to the GPA, translate the GPA to a host physical address (HPA) of the memory page, store, in a translation lookaside buffer (TLB), a TLB entry mapping the GVA to the HPA, modify the GPT entry to designate the memory page as accessed, detect an attempt by an application to modify the GPT entry; generate, in response to the attempt to modify the GPT entry, a page fault; and flush, in response to the page fault, the TLB entry.

公开(公告)号：US20200097313A1

公开(公告)日：2020-03-26

申请号：US16333987

申请日：2019-02-22

Applicant: INTEL CORPORATION

Inventor： Chuanxiao Dong ,  Yaozu Dong ,  Zhiyuan Lv ,  Zhi Wang

IPC: G06F9/455 ,  G06F9/48

Abstract: Implementations disclosed describe a system and a method to execute a virtual machine on a processing device, receive a request to access a memory page identified by a guest virtual memory address (GVA) in an address space of the virtual machine, translate the GVA to a guest physical memory address (GPA) using a guest page table (GPT) comprising a GPT entry mapping the GVA to the GPA, translate the GPA to a host physical address (HPA) of the memory page, store, in a translation lookaside buffer (TLB), a TLB entry mapping the GVA to the HPA, modify the GPT entry to designate the memory page as accessed, detect an attempt by an application to modify the GPT entry; generate, in response to the attempt to modify the GPT entry, a page fault; and flush, in response to the page fault, the TLB entry.