公开(公告)号：US09811145B2

公开(公告)日：2017-11-07

申请号：US13720531

申请日：2012-12-19

Applicant: Intel Corporation

Inventor： Huimin Chen ,  Kok Hong Chan ,  Kian Leong Phang ,  Karthi Vadivelu

IPC: G06F1/32 ,  G06F13/40 ,  G06F1/26

CPC classification number: G06F1/3253 ,  G06F1/26 ,  G06F1/3215 ,  G06F1/3278 ,  G06F13/4022 ,  Y02D10/151 ,  Y02D10/157

Abstract: Techniques for reducing idle power consumption of a port are described herein. An example method includes determining device presence using a pull-down resistor disposed in a downstream port. The method also includes initiating a low power state of a link between the downstream port and an upstream device. The method also includes disabling the pull-down resistor in response to initiating the low power state.

公开(公告)号：US20170262402A1

公开(公告)日：2017-09-14

申请号：US15607367

申请日：2017-05-26

Applicant: INTEL CORPORATION

Inventor： Huimin Chen ,  Duane G. Quiet

IPC: G06F13/42

CPC classification number: G06F13/4291

Abstract: A system and method is described for simplifying implementation of repeater (e.g., re-driver/re-timer) module implementation in high-data-rate interconnects that carry a relatively low-data-rate clock signal as well as the data stream (e.g., PCIe). At the endpoint, any information critical to the function of the repeater (e.g., the most recent data rate negotiated by a pair of endpoints communicating through the repeater) is embedded in the clock signal by pulse-width modulation as ordered sets. The repeater only needs to read the clock-embedded information rather than decoding the data stream. Thus repeaters for such applications reconstruct the high-rate data-stream while actually decoding only the low-rate clock signal. Because the clock-signal protocol is independent of the data-stream protocol, the repeater's operation is protocol-agnostic with respect to the data-stream.

公开(公告)号：US20170262401A1

公开(公告)日：2017-09-14

申请号：US15607362

申请日：2017-05-26

Applicant: INTEL CORPORATION

Inventor： Huimin Chen ,  Duane G. Quiet

IPC: G06F13/42

CPC classification number: G06F13/4291 ,  G06F13/4072 ,  G06F13/4295 ,  G06F2213/0026 ,  Y02D10/14 ,  Y02D10/151

Abstract: A system and method is described for simplifying implementation of repeater (e.g., re-driver/re-timer) module implementation in high-data-rate interconnects that carry a relatively low-data-rate clock signal as well as the data stream (e.g., PCIe). At the endpoint, any information critical to the function of the repeater (e.g., the most recent data rate negotiated by a pair of endpoints communicating through the repeater) is embedded in the clock signal by pulse-width modulation as ordered sets. The repeater only needs to read the clock-embedded information rather than decoding the data stream. Thus repeaters for such applications reconstruct the high-rate data-stream while actually decoding only the low-rate clock signal. Because the clock-signal protocol is independent of the data-stream protocol, the repeater's operation is protocol-agnostic with respect to the data-stream.

公开(公告)号：US20160196233A1

公开(公告)日：2016-07-07

申请号：US14672168

申请日：2015-03-28

Applicant: Intel Corporation

Inventor： Huimin Chen ,  Duane G. Quiet

IPC: G06F13/42 ,  H04L27/32

CPC classification number: G06F13/4291

Abstract: A system and method is described for simplifying implementation of repeater (e.g., re-driver/re-timer) module implementation in high-data-rate interconnects that carry a relatively low-data-rate clock signal as well as the data stream (e.g., PCIe). At the endpoint, any information critical to the function of the repeater (e.g., the most recent data rate negotiated by a pair of endpoints communicating through the repeater) is embedded in the clock signal by pulse-width modulation as ordered sets. The repeater only needs to read the clock-embedded information rather than decoding the data stream. Thus repeaters for such applications reconstruct the high-rate data-stream while actually decoding only the low-rate clock signal. Because the clock-signal protocol is independent of the data-stream protocol, the repeater's operation is protocol-agnostic with respect to the data-stream.

Abstract translation: 描述了一种系统和方法，用于简化在承载相对低数据速率时钟信号以及数据流（例如，数据速率）的高数据速率互连中的中继器（例如，重新驱动/重新定时器）模块的实现。 ，PCIe）。 在端点处，对于中继器功能至关重要的任何信息（例如，通过中继器通信的一对端点协商的最新数据速率）通过脉冲宽度调制作为有序集合被嵌入到时钟信号中。 中继器只需要读取时钟嵌入信息，而不是解码数据流。 因此，用于这种应用的中继器重建高速率数据流，同时仅实现仅解码低速率时钟信号。 由于时钟信号协议独立于数据流协议，所以中继器的操作与数据流相比是协议无关的。

公开(公告)号：US20160092381A1

公开(公告)日：2016-03-31

申请号：US14498474

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： Huimin Chen ,  Keith A. Jones ,  John L. Baudrexl ,  Ronald W. Swartz ,  Vui Yong Liew

IPC: G06F13/22 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F13/22 ,  G06F13/4054 ,  G06F13/4286

Abstract: A first state of an interconnect protocol is entered. A particular signal is sent according to the protocol to a device over a link. During the first state, it is detected that a response to the particular signal is received in the first state. It is determined that the device supports a configuration mode outside the protocol based on the received response. The configuration mode is entered based on the response. One or more in-band configuration messages are sent within the configuration mode.

Abstract translation: 输入互连协议的第一状态。 根据协议将特定信号发送到通过链路的设备。 在第一状态期间，检测到在第一状态下接收到对特定信号的响应。 确定设备基于接收到的响应支持协议之外的配置模式。 基于响应输入配置模式。 在配置模式下发送一个或多个带内配置消息。

公开(公告)号：US09201831B2

公开(公告)日：2015-12-01

申请号：US13730672

申请日：2012-12-28

Applicant: Intel Corporation

Inventor： Kok Hong Chan ,  Huimin Chen

IPC: G06F13/40

CPC classification number: G06F13/4221 ,  G06F1/3296 ,  G06F13/4022 ,  G06F13/4027 ,  G06F2213/0042 ,  G06F2213/4004 ,  Y02D10/14 ,  Y02D10/151

Abstract: A method and system for communicating data between two devices are described herein. The method detects an electrical signal of a first protocol from a first device in a repeater, wherein the first protocol comprises single-ended signaling. The method also determines the speed of the electrical signal. Additionally, the method converts the electrical signal of the first protocol into an electrical signal of a second protocol based on the speed of the electrical signal. The second protocol comprises differential signaling. Furthermore, the method sends the electrical signal of the second protocol to a second device. In addition, the method stops the electrical signal of the second protocol to the second device when the electrical signal of the second protocol indicates an end of data flow.

Abstract translation: 这里描述了用于在两个设备之间传送数据的方法和系统。 该方法从中继器中的第一设备检测第一协议的电信号，其中第一协议包括单端信令。 该方法还确定电信号的速度。 此外，该方法基于电信号的速度将第一协议的电信号转换为第二协议的电信号。 第二协议包括差分信令。 此外，该方法将第二协议的电信号发送到第二设备。 此外，当第二协议的电信号指示数据流的结束时，该方法将第二协议的电信号停止到第二设备。

公开(公告)号：US09191192B2

公开(公告)日：2015-11-17

申请号：US13856484

申请日：2013-04-04

Applicant: INTEL CORPORATION

Inventor： Huimin Chen ,  Chunyu Zhang ,  Paul S. Durley

IPC: H04B1/38 ,  H04L7/033 ,  H04L25/49 ,  H04L7/00

CPC classification number: H04L7/033 ,  H04L7/0004 ,  H04L7/0331 ,  H04L25/4904

Abstract: Systems and methods of operating a serial interconnect interface provide for generating a pulse in response to a state change in a data signal of the serial interface interconnect, and transmitting the pulse from a physical layer of the serial interconnect interface to a link layer of the serial interconnect interface. The duration of the pulse can be selected based on whether the state change corresponds to an end of packet (EOP) condition. In addition, the data signal may include a non return to zero invert (NRZI) encoded signal, wherein the pulse is part of a digital NRZI signal.

Abstract translation: 操作串行互连接口的系统和方法提供响应于串行接口互连的数据信号中的状态改变而产生脉冲，以及将脉冲从串行互连接口的物理层发送到串行接口互连的链路层 互连接口。 可以基于状态改变是否对应于分组结束（EOP）条件来选择脉冲的持续时间。 另外，数据信号可以包括不返回到零反转（NRZI）编码信号，其中脉冲是数字NRZI信号的一部分。

公开(公告)号：US09129066B2

公开(公告)日：2015-09-08

申请号：US14176653

申请日：2014-02-10

Applicant: INTEL CORPORATION

Inventor： Kok Hong Chan ,  Huimin Chen

IPC: G06F3/00 ,  G06F13/38 ,  G06F11/30

CPC classification number: G06F13/385 ,  G06F1/266 ,  G06F1/3209 ,  G06F1/3215 ,  G06F1/3253 ,  G06F11/3041 ,  G06F11/3051 ,  G06F11/3055 ,  G06F13/4282 ,  G06F2213/0042 ,  Y02D10/14 ,  Y02D10/151

Abstract: Systems and methods for operating a universal serial bus are described herein. The method includes sending packet data from a USB2 device to a USB2 host on a pair of signal lines, and after sending the packet data, sending an End-Of-Packet (EOP) signal from the USB2 device to the USB2 host. The method also includes, entering the USB2 device into idle state after sending the EOP signal. The method also includes sending a digital ping from the USB2 device to the USB2 host to indicate device presence during idle state.

Abstract translation: 这里描述了用于操作通用串行总线的系统和方法。 该方法包括从USB2设备向一对信号线上的USB2主机发送分组数据，并且在发送分组数据之后，从USB2设备向USB2主机发送分组结束（EOP）信号。 该方法还包括在发送EOP信号后进入空闲状态的USB2设备。 该方法还包括从USB2设备向USB2主机发送数字ping，以指示在空闲状态下的设备存在。

公开(公告)号：US20150227489A1

公开(公告)日：2015-08-13

申请号：US14457594

申请日：2014-08-12

Applicant: INTEL CORPORATION

Inventor： Huimin Chen ,  Jia Jun Lee ,  Amit Kumar Srivastava ,  Teong Guan T.G. Yew ,  Tim McKee

IPC: G06F13/42

CPC classification number: G06F13/4291 ,  G06F13/385

Abstract: Techniques for embedded high speed serial interface methods are described herein. The method includes issuing a single-ended one (SE1) signal on each of a pair of embedded high speed serial interface data lines, the SE1 indicating a register access protocol (RAP) message follows the SE1 signal. The method also includes accessing a register of an embedded high speed serial interface component based on the RAP message.

Abstract translation: 本文描述了嵌入式高速串行接口方法的技术。 该方法包括在一对嵌入式高速串行接口数据线中的每一个上发出单端（SE1）信号，指示寄存器访问协议（RAP）消息的SE1跟随SE1信号。 该方法还包括基于RAP消息访问嵌入式高速串行接口组件的寄存器。

公开(公告)号：US08977789B2

公开(公告)日：2015-03-10

申请号：US13730188

申请日：2012-12-28

Applicant: Intel Corporation

Inventor： Kok Hong Chan ,  Huimin Chen

IPC: G06F13/20 ,  G06F13/38 ,  G06F13/42

CPC classification number: G06F13/385 ,  G06F13/4295 ,  Y02D10/14 ,  Y02D10/151

Abstract: Systems and methods for detecting Input/Output (I/O) device connection are described herein. The method includes physically coupling an I/O device to a host port through a first signal line and a second signal line. The method also includes driving the first signal line or the second signal line high via an active buffer of the I/O device. The method also includes providing an acknowledgement signal from the host to the device through the other signal line that is not being driven high by the active buffer of the I/O device.

Abstract translation: 本文描述了用于检测输入/输出（I / O）设备连接的系统和方法。 该方法包括通过第一信号线和第二信号线将I / O设备物理耦合到主机端口。 该方法还包括经由I / O设备的主动缓冲器驱动第一信号线或第二信号线为高电平。 该方法还包括通过不被I / O设备的主动缓冲器驱动为高电平的另一条信号线，将来自主机的确认信号提供给设备。