公开(公告)号：US20210200685A1

公开(公告)日：2021-07-01

申请号：US16729371

申请日：2019-12-28

Applicant: Intel Corporation

Inventor： Ron Gabor ,  Enrico Perla ,  Raanan Sade ,  Igor Yanover ,  Tomar Stark

IPC: G06F12/0895 ,  G06F12/1009 ,  G06F12/14 ,  G06F12/1045

Abstract: An apparatus and method for tagged memory management, an embodiment including execution circuitry to generate a system memory access request having a first address pointer and address translation circuitry to determine whether to translate the first address pointer with metadata processing. The address translation circuitry is to access address translation tables to translate the first address pointer to a first physical address, perform a lookup in a memory metadata table to identify a memory metadata value associated with a physical address range including the first physical address, determine a pointer metadata value associated with the first address pointer, and compare the memory metadata value with the pointer metadata value; and when the comparison results in a validation of the memory access request, then return the first physical address.

公开(公告)号：US10976961B2

公开(公告)日：2021-04-13

申请号：US16228374

申请日：2018-12-20

Applicant: Intel Corporation

Inventor： Ron Gabor ,  Tomer Stark ,  Joseph Nuzman ,  Ady Tal

IPC: G06F9/34 ,  G06F3/06 ,  G06F11/07 ,  G06F9/38

Abstract: Techniques and mechanisms for circuitry of a processor to automatically provide, and perform an operation based on, metadata indicating an uninitialized memory block. In an embodiment, processor circuitry detects a software instruction which specifies a first operation to be performed based on some data at a memory block. Metadata corresponding to said data comprises an identifier of whether the data is based on an uninitialized memory condition. Processing of the instruction, includes the processor circuitry automatically performing a second operation based on the identifier. The second operation is performed independent of any instruction of the application which specifies the second operation. In another embodiment, execution of the instruction (if any) is conditional upon an evaluation which is based on the state identifier, or the second operation is automatically performed based on an execution of the first instruction.

公开(公告)号：US10891230B1

公开(公告)日：2021-01-12

申请号：US16458017

申请日：2019-06-29

Applicant: Intel Corporation

Inventor： Ron Gabor ,  Igor Yanover

IPC: G06F9/34 ,  G06F12/0811

Abstract: Systems, methods, and apparatuses relating to linear address masking architecture are described. In one embodiment, a hardware processor includes an address generation unit to generate a linear address for a memory access request to a memory, at least one control register comprising a user mode masking bit and a supervisor mode masking bit, a register comprising a current privilege level indication, and a memory management unit to mask out a proper subset of bits inside an address space of the linear address for the memory access request based on the current privilege level indication and either of the user mode masking bit or the supervisor mode masking bit to produce a resultant linear address, and output the resultant linear address.

公开(公告)号：US20190235948A1

公开(公告)日：2019-08-01

申请号：US16224579

申请日：2018-12-18

Applicant: Intel Corporation

Inventor： Tomer Stark ,  Ron Gabor ,  Joseph Nuzman ,  Raanan Sade ,  Bryant E. Bigbee

IPC: G06F11/07 ,  G06F12/109 ,  G06F9/38 ,  G06F12/00

CPC classification number: G06F11/0751 ,  G06F9/38 ,  G06F11/073 ,  G06F12/00 ,  G06F12/109 ,  G06F12/145 ,  G06F21/60 ,  G06F2212/1032 ,  G06F2212/1052 ,  G06F2212/656

Abstract: Methods and apparatuses relating to memory corruption detection are described. In one embodiment, a hardware processor includes an execution unit to execute an instruction to request access to a block of a memory through a pointer to the block of the memory, and a memory management unit to allow access to the block of the memory when a memory corruption detection value in the pointer is validated with a memory corruption detection value in the memory for the block, wherein a position of the memory corruption detection value in the pointer is selectable between a first location and a second, different location.

公开(公告)号：US20190227951A1

公开(公告)日：2019-07-25

申请号：US16369880

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： David M. Durham ,  Ron Gabor

IPC: G06F12/14 ,  G06F21/60 ,  G06F21/62 ,  G06F21/57

Abstract: Embodiments are directed to memory protection with hidden inline metadata. An embodiment of an apparatus includes processor cores; a computer memory for the storage of data; and cache memory communicatively coupled with one or more of the processor cores, wherein one or more processor cores of the plurality of processor cores are to implant hidden inline metadata in one or more cachelines for the cache memory, the hidden inline metadata being hidden at a linear address level.

公开(公告)号：US10095573B2

公开(公告)日：2018-10-09

申请号：US15708079

申请日：2017-09-18

Applicant: Intel Corporation

Inventor： Tomer Stark ,  Ady Tal ,  Ron Gabor ,  Joseph Nuzman

IPC: G06F11/07 ,  G06F11/10

Abstract: Memory corruption detection technologies are described. A processor can include a memory to store a memory corruption detection (MCD) table. A processor core of the processor can receive, from an application, an allocation request for an allocation of a memory object within a contiguous memory block in the memory. The processor core can allocate the contiguous memory block in view of a size of the memory object requested and write MCD meta-data into the MCD table, including a MCD identifier (ID) associated with the contiguous memory block and a MCD border value indicating a size of a memory region of the contiguous memory block.

公开(公告)号：US10073727B2

公开(公告)日：2018-09-11

申请号：US14635896

申请日：2015-03-02

Applicant: Intel Corporation

Inventor： Tomer Stark ,  Ady Tal ,  Ron Gabor

IPC: G06F11/10 ,  G06F11/07

CPC classification number: G06F11/079 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/0772 ,  G06F11/10 ,  G06F11/1064

Abstract: Memory corruption detection technologies are described. A method can include receiving, from the application, an allocation request for an allocation of one or more contiguous memory blocks of the memory for a memory object. The method can further include allocating, by a processor, the one or more contiguous memory blocks for the memory object in view of a size of the memory object requested. The method can further include writing, into a MCD table, a first memory corruption detection (MCD) unique identifier associated with the one or more contiguous memory blocks. The method can further include creating a pointer with a memory address of the memory object and a second MCD unique identifier associated with the memory object. The method can further include sending, to the application, the pointer.

公开(公告)号：US20180196706A1

公开(公告)日：2018-07-12

申请号：US15402835

申请日：2017-01-10

Applicant: Intel Corporation

Inventor： Alex Gerber ,  Yiannakis Sazeides ,  Arkady Bramnik ,  Ron Gabor

IPC: G06F11/07

CPC classification number: G06F11/079 ,  G06F11/0721 ,  G06F11/0727 ,  G06F11/0751

Abstract: A processor includes physical storage locations, and a register rename unit that includes a plurality of register rename storage structures. At a given time, each of a complete group of physical storage location identifiers is to be stored in one, but only one, of the plurality of register rename storage structures, unless there is an error. Each of the complete group of physical storage location identifiers is to identify a different one of the physical storage locations. The register rename unit is to detect an error when a first value, which is to be equal to an operation on the complete group of the physical storage location identifiers with no errors, is inconsistent with a second value. The second value is to represent the operation on all physical storage location identifiers that are to be stored in the plurality of register rename storage structures at the given time.

公开(公告)号：US20180129265A1

公开(公告)日：2018-05-10

申请号：US15849836

申请日：2017-12-21

Applicant: Intel Corporation

Inventor： Nadav Bonen ,  Ron Gabor ,  Zeev Sperber ,  Vjekoslav Svilan ,  David N. Mackintosh ,  Jose A. Baiocchi Paredes ,  Naveen Kumar ,  Shantanu Gupta

IPC: G06F1/32 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F1/3243 ,  G06F1/3287 ,  G06F9/30083 ,  G06F9/3869 ,  G06F9/3885 ,  Y02B70/123 ,  Y02B70/126 ,  Y02D10/152 ,  Y02D10/171

Abstract: In an embodiment, the present invention includes an execution unit to execute instructions of a first type, a local power gate circuit coupled to the execution unit to power gate the execution unit while a second execution unit is to execute instructions of a second type, and a controller coupled to the local power gate circuit to cause it to power gate the execution unit when an instruction stream does not include the first type of instructions. Other embodiments are described and claimed.

公开(公告)号：US20180004595A1

公开(公告)日：2018-01-04

申请号：US15201438

申请日：2016-07-02

Applicant: Intel Corporation

Inventor： Ashok Raj ,  Ron Gabor ,  Hisham Shafi ,  Sergiu Ghetie ,  Mohan J. Kumar ,  Theodros Yigzaw ,  Sarathy Jayakumar ,  Neeraj S. Upasani

IPC: G06F11/10 ,  G06F12/0893 ,  G06F12/1045 ,  G06F12/0875 ,  G06F3/06

CPC classification number: G06F11/1048 ,  G06F11/0721

Abstract: A processor of an aspect includes a decode unit to decode a read from memory instruction. The read from memory instruction is to indicate a source memory operand and a destination storage location. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the read from memory instruction, is to read data from the source memory operand, store an indication of defective data in an architecturally visible storage location, when the data is defective, and complete execution of the read from memory instruction without causing an exceptional condition, when the data is defective. Other processors, methods, systems, and instructions are disclosed.