公开(公告)号：US10142098B2

公开(公告)日：2018-11-27

申请号：US15196698

申请日：2016-06-29

Applicant: Intel Corporation

Inventor： Vikram B. Suresh ,  Sudhir K. Satpathy ,  Sanu K. Mathew

IPC: H04L9/32 ,  H04L9/06 ,  G09C1/00

Abstract: A processing system includes a processor to construct an input message comprising a plurality of padding bits and a hardware accelerator, communicatively coupled to the processor, comprising a first plurality of circuits to perform a stage-1 secure hash algorithm (SHA) hash based on the input message, wherein the hardware accelerator comprises a first data path coupled between a first reference node and a first input node of the first plurality of circuits to feed a first padding bit of the plurality of padding bits to the first input node.

公开(公告)号：US10103877B2

公开(公告)日：2018-10-16

申请号：US14864227

申请日：2015-09-24

Applicant: Intel Corporation

Inventor： Sudhir K. Satpathy ,  Sanu K. Mathew ,  Kirk S. Yap ,  Vinodh Gopal

IPC: G06F9/30 ,  G06F21/60 ,  H04L9/28 ,  H04L9/06 ,  H04L9/14

Abstract: A processing system includes a memory and a processing logic operatively coupled to the memory. The processing logic identifies one or more constant bits of an output bit sequence. The processing logic generates a plurality of variable bits of the output bit sequence. The processing logic produces the output bit sequence including the identified constant bits and the generated plurality of variable bits.

公开(公告)号：US10103873B2

公开(公告)日：2018-10-16

申请号：US15088823

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Raghavan Kumar ,  Sanu K. Mathew ,  Sudhir K. Satpathy ,  Vikram B. Suresh

IPC: G06F11/30 ,  H04L9/00 ,  H04L9/06 ,  G06F12/14

Abstract: A processing system includes a processing core and a hardware accelerator communicatively coupled to the processing core. The hardware accelerator includes a random number generator to generate a byte order indicator. The hardware accelerator also includes a first switching module communicatively coupled to the random value indicator generator. The switching module receives an byte sequence in an encryption round of the cryptographic operation and feeds a portion of the input byte sequence to one of a first substitute box (S-box) module or a second S-box module in view of a byte order indicator value generated by the random number generator.

公开(公告)号：US10027472B2

公开(公告)日：2018-07-17

申请号：US15277856

申请日：2016-09-27

Applicant: Intel Corporation

Inventor： Vikram B. Suresh ,  Sanu K. Mathew ,  Sudhir K. Satpathy

IPC: H03K19/00 ,  H04L9/00 ,  H03K19/003 ,  G06N99/00

Abstract: Embodiments include apparatuses, methods, and systems for a physically unclonable function (PUF) circuit. The PUF circuit may include an array of PUF cells to generate respective response bits of an authentication code in response to a challenge bit string. The PUF cells may include a pair of cross-coupled inverters, the individual inverters including independently selectable pull-down or pull-up legs. One of the pull-up or pull-down legs of each inverter may be selectively activated based on the challenge bit string. The PUF cells may further include first and second configurable clock delay circuits to pass respective clock signals to pre-charge transistors of the PUF cell. A dark bit masking circuit may generate a soft dark bit mask for the PUF circuit. Other embodiments may be described and claimed.

公开(公告)号：US10020934B2

公开(公告)日：2018-07-10

申请号：US14933011

申请日：2015-11-05

Applicant: Intel Corporation

Inventor： Vikram B. Suresh ,  Sudhir K. Satpathy ,  Sanu K. Mathew

IPC: H04L9/06 ,  H04L9/32

CPC classification number: H04L9/0643 ,  G06F9/3895 ,  H04L9/3239 ,  H04L2209/12 ,  H04L2209/125

Abstract: In an embodiment, a processor includes a hardware accelerator to receive a message to be processed using the cryptographic hash algorithm; store a plurality of digest words in a plurality of digest registers; perform a plurality of rounds of the cryptographic hash algorithm, where the plurality of rounds is divided into first and second sets of rounds; in each cycle of each round in the first set, use W bits from the first digest register for a first function and use N bits from the second digest register for a second function; in each cycle of each round in the second set, use W bits from the second digest register for the first function and use N bits from the first digest register for the second function. Other embodiments are described and claimed.

公开(公告)号：US09996708B2

公开(公告)日：2018-06-12

申请号：US14751995

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Sudhir K. Satpathy ,  Sanu K. Mathew ,  Kirk S. Yap ,  Vinodh Gopal

IPC: G06F11/30 ,  G06F12/14 ,  G06F21/74 ,  G09C1/00 ,  H04L9/06

CPC classification number: G06F21/74 ,  G06F21/73 ,  G06F2221/2107 ,  G09C1/00 ,  H04L9/0631 ,  H04L2209/122

Abstract: A processing system includes a processing core and a hardware accelerator communicatively coupled to the processing core. The hardware accelerator includes a data register having a plurality of data bits and a key register having a plurality of key bits. The hardware accelerator also includes a data mode selector module to select one of an encrypt mode or a decrypt mode for processing the plurality of data bits. The hardware accelerator further includes a key mode selector module to select one of the encrypt mode or the decrypt mode for processing the plurality of key bits.

公开(公告)号：US20180097618A1

公开(公告)日：2018-04-05

申请号：US15283000

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Raghavan Kumar ,  Sanu K. Mathew ,  Avinash L. Varna ,  Vikram B. Suresh ,  Sudhir K. Satpathy

IPC: H04L9/06 ,  G11C19/00 ,  H03K19/21 ,  H04L9/00 ,  H04L9/08

CPC classification number: H04L9/0662 ,  G09C1/00 ,  G11C19/00 ,  H03K19/215 ,  H04L9/003 ,  H04L9/0631 ,  H04L2209/046 ,  H04L2209/125

Abstract: Described is an apparatus comprising an S-box circuitry operable to convert a value on an input into a value on an output in accordance with an Advanced Encryption Standard (AES) Rijndael S-box matrix. The apparatus also comprises a pseudo-random number generation (PRG) circuitry operable to provide a sequence of pseudo-random numbers on a first output and a registered copy of the sequence on a second output. The apparatus further comprises a mask circuitry operable to provide an XOR of a value on the output of the S box circuitry and a value on the first output of the PRG circuitry. The apparatus additionally comprises a mask removal circuitry operable to provide an XOR of a value on an output of the data register circuitry, a value coupled to an output of a key register circuitry, and a value on the second output of the PRG circuitry.

公开(公告)号：US20180089433A1

公开(公告)日：2018-03-29

申请号：US15277195

申请日：2016-09-27

Applicant: Intel Corporation

Inventor： Sanu K. Mathew ,  Sudhir K. Satpathy ,  Vikram B. Suresh ,  Patrick Koeberl

IPC: G06F21/56 ,  H01L27/02 ,  G06F21/72

CPC classification number: G06F21/567 ,  G06F21/72 ,  G06F21/75 ,  H01L23/573 ,  H01L27/0207

Abstract: Some embodiments include apparatuses having diffusion regions located adjacent each other in a substrate, and connections coupled to the diffusion regions. The diffusion regions include first diffusion regions, second diffusion regions, and third diffusion regions. One of the second diffusion regions and one of the third diffusion regions are between two of the first diffusion regions. One of the first diffusion regions and one of the third diffusion regions are between two of the second diffusion regions. The connections include a first connection coupled to each of the first diffusion regions, a second connection coupled to each of the second diffusion regions, and a third connection coupled to each of the third diffusion regions.

公开(公告)号：US09928036B2

公开(公告)日：2018-03-27

申请号：US14865009

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Sanu K. Mathew ,  David Johnston ,  Sudhir K. Satpathy

IPC: G06F7/58

CPC classification number: G06F7/588 ,  G06F7/483 ,  G06F2207/58 ,  H04L9/0637 ,  H04L9/0869

Abstract: A processor includes an execution unit to generate a random number. The execution unit includes entropy source circuits, correlation circuits, and an extractor circuit. The entropy source circuits include all-digital components and are to generate an initial randomized bit stream. The correlation circuits are to remove correlations from the initial randomized bit stream to yield an intermediate randomized bit stream. The extractor circuit is to select a subset of the intermediate randomized bit stream as a random output of the execution unit.

公开(公告)号：US09910792B2

公开(公告)日：2018-03-06

申请号：US15095783

申请日：2016-04-11

Applicant: Intel Corporation

Inventor： Sudhir K. Satpathy ,  Sanu K. Mathew ,  Vikram B. Suresh

IPC: H04L9/06 ,  G06F12/14 ,  H04L9/30

CPC classification number: G06F12/1408 ,  G06F21/00 ,  G06F21/72 ,  G06F2212/1052 ,  G09C1/00 ,  H04L9/0631 ,  H04L9/3093 ,  H04L2209/12 ,  H04L2209/24

Abstract: A processing system includes a memory and a cryptographic accelerator operatively coupled to the memory. The cryptographic accelerator performs a split substitute byte operation within two paths of a cryptographic round by determining a first output from a first path by applying a mapped affine transformation to an input bit sequence represented by an element of a composite field of a finite-prime field, wherein the first output is represented by a first element of the composite field of the finite-prime field, and a second output from a second path by applying a scaled mapped affine transformation to the input bit sequence, wherein the second output is represented by a second element of the composite field and is equal to a multiple of the first output in the composite field.