公开(公告)号：US20150089195A1

公开(公告)日：2015-03-26

申请号：US14556931

申请日：2014-12-01

Applicant: Intel Corporation

Inventor： Vinodh Gopal ,  James D. Guilford ,  Erdinc Ozturk ,  Wajdi K. Feghali ,  Gilbert M. Wolrich ,  Martin G. Dixon

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/30145 ,  G06F9/3001 ,  G06F9/30029 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30167 ,  G06F9/3816 ,  G06F9/3893

Abstract: Method and apparatus for performing a shift and XOR operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources perform a shift and XOR on at least one value.

Abstract translation: 执行换档和异或运算的方法和装置。 在一个实施例中，一种装置包括执行第一指令的执行资源。 响应于第一指令，所述执行资源对至少一个值执行移位和异或。

公开(公告)号：US20140122839A1

公开(公告)日：2014-05-01

申请号：US13997186

申请日：2011-12-22

Applicant: INTEL CORPORATION

Inventor： Gilbert M. Wolrich ,  Kirk S. Yap ,  James D. Guilford ,  Erdinc Ozturk ,  Vinodh Gopal ,  Wajdi K. Feghali ,  Sean M. Gulley ,  Martin G. Dixon

IPC: G06F9/30

CPC classification number: G06F9/30029 ,  G06F9/30007 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/3885 ,  G06F9/3895 ,  H04L9/0643

Abstract: An apparatus is described that includes an execution unit within an instruction pipeline. The execution unit has multiple stages of a circuit that includes a) and b) as follows. a) a first logic circuitry section having multiple mix logic sections each having: i) a first input to receive a first quad word and a second input to receive a second quad word; ii) an adder having a pair of inputs that are respectively coupled to the first and second inputs; iii) a rotator having a respective input coupled to the second input; iv) an XOR gate having a first input coupled to an output of the adder and a second input coupled to an output of the rotator. b) permute logic circuitry having inputs coupled to the respective adder and XOR gate outputs of the multiple mix logic sections.

Abstract translation: 描述了包括指令流水线内的执行单元的装置。 执行单元具有包括a）和b）的电路的多个级，如下所述。 a）具有多个混合逻辑部分的第一逻辑电路部分，每个混合逻辑部分具有：i）用于接收第一四进制字的第一输入和用于接收第二四字的第二输入; ii）具有分别耦合到第一和第二输入的一对输入的加法器; iii）具有耦合到第二输入的相应输入的旋转器; iv）具有耦合到加法器的输出的第一输入和耦合到转子的输出的第二输入的异或门。 b）具有耦合到多个混合逻辑部分的相应加法器和异或门输出的输入的置换逻辑电路。

公开(公告)号：US12175246B2

公开(公告)日：2024-12-24

申请号：US18460497

申请日：2023-09-01

Applicant: Intel Corporation

Inventor： Dan Baum ,  Michael Espig ,  James Guilford ,  Wajdi K. Feghali ,  Raanan Sade ,  Christopher J. Hughes ,  Robert Valentine ,  Bret Toll ,  Elmoustapha Ould-Ahmed-Vall ,  Mark J. Charney ,  Vinodh Gopal ,  Ronen Zohar ,  Alexander F. Heinecke

IPC: G06F9/30 ,  G06F9/38

Abstract: Disclosed embodiments relate to matrix compress/decompress instructions. In one example, a processor includes fetch circuitry to fetch a compress instruction having a format with fields to specify an opcode and locations of decompressed source and compressed destination matrices, decode circuitry to decode the fetched compress instructions, and execution circuitry, responsive to the decoded compress instruction, to: generate a compressed result according to a compress algorithm by compressing the specified decompressed source matrix by either packing non-zero-valued elements together and storing the matrix position of each non-zero-valued element in a header, or using fewer bits to represent one or more elements and using the header to identify matrix elements being represented by fewer bits; and store the compressed result to the specified compressed destination matrix.

公开(公告)号：US11900108B2

公开(公告)日：2024-02-13

申请号：US17461949

申请日：2021-08-30

Applicant: Intel Corporation

Inventor： Vinodh Gopal ,  James D. Guilford ,  Gilbert M. Wolrich ,  Wajdi K. Feghali ,  Erdinc Ozturk ,  Martin G. Dixon ,  Sean P. Mirkes ,  Bret L. Toll ,  Maxim Loktyukhin ,  Mark C. Davis ,  Alexandre J. Farcy

IPC: G06F9/30

CPC classification number: G06F9/30032 ,  G06F9/30094 ,  G06F9/30098

Abstract: A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand indicated by the rotate instruction. The result may have the source operand rotated by the rotate amount. Execution of the rotate instruction may complete without reading a carry flag.

公开(公告)号：US20210036848A1

公开(公告)日：2021-02-04

申请号：US16928558

申请日：2020-07-14

Applicant: Intel Corporation

Inventor： Sean M. Gulley ,  Gilbert M. Wolrich ,  Vinodh Gopal ,  Kirk S. Yap ,  Wajdi K. Feghali

IPC: H04L9/08 ,  H04L9/06 ,  G06F21/72 ,  G06F9/30 ,  G09C1/00 ,  G06F9/38

Abstract: Instructions and logic provide for a Single Instruction Multiple Data (SIMD) SM4 round slice operation. Embodiments of an instruction specify a first and a second source data operand set, and substitution function indicators, e.g. in an immediate operand. Embodiments of a processor may include encryption units, responsive to the first instruction, to: perform a slice of SM4-round exchanges on a portion of the first source data operand set with a corresponding keys from the second source data operand set in response to a substitution function indicator that indicates a first substitution function, perform a slice of SM4 key generations using another portion of the first source data operand set with corresponding constants from the second source data operand set in response to a substitution function indicator that indicates a second substitution function, and store a set of result elements of the first instruction in a SIMD destination register.

公开(公告)号：US10778425B2

公开(公告)日：2020-09-15

申请号：US16223109

申请日：2018-12-17

Applicant: Intel Corporation

Inventor： Sean M. Gulley ,  Gilbert M. Wolrich ,  Vinodh Gopal ,  Kirk S. Yap ,  Wajdi K. Feghali

IPC: H04L9/08 ,  H04L9/06 ,  G06F21/72 ,  G06F9/30 ,  G09C1/00 ,  G06F9/38

Abstract: Instructions and logic provide for a Single Instruction Multiple Data (SIMD) SM4 round slice operation. Embodiments of an instruction specify a first and a second source data operand set, and substitution function indicators, e.g. in an immediate operand. Embodiments of a processor may include encryption units, responsive to the first instruction, to: perform a slice of SM4-round exchanges on a portion of the first source data operand set with a corresponding keys from the second source data operand set in response to a substitution function indicator that indicates a first substitution function, perform a slice of SM4 key generations using another portion of the first source data operand set with corresponding constants from the second source data operand set in response to a substitution function indicator that indicates a second substitution function, and store a set of result elements of the first instruction in a SIMD destination register.

公开(公告)号：US10719323B2

公开(公告)日：2020-07-21

申请号：US16144902

申请日：2018-09-27

Applicant: Intel Corporation

Inventor： Dan Baum ,  Michael Espig ,  James Guilford ,  Wajdi K. Feghali ,  Raanan Sade ,  Christopher J. Hughes ,  Robert Valentine ,  Bret Toll ,  Elmoustapha Ould-Ahmed-Vall ,  Mark J. Charney ,  Vinodh Gopal ,  Ronen Zohar ,  Alexander F. Heinecke

IPC: G06F9/30 ,  G06F9/38

Abstract: Disclosed embodiments relate to matrix compress/decompress instructions. In one example, a processor includes fetch circuitry to fetch a compress instruction having a format with fields to specify an opcode and locations of decompressed source and compressed destination matrices, decode circuitry to decode the fetched compress instructions, and execution circuitry, responsive to the decoded compress instruction, to: generate a compressed result according to a compress algorithm by compressing the specified decompressed source matrix by either packing non-zero-valued elements together and storing the matrix position of each non-zero-valued element in a header, or using fewer bits to represent one or more elements and using the header to identify matrix elements being represented by fewer bits; and store the compressed result to the specified compressed destination matrix.

公开(公告)号：US10691458B2

公开(公告)日：2020-06-23

申请号：US15716258

申请日：2017-09-26

Applicant: Intel Corporation

Inventor： Kirk S. Yap ,  Gilbert Wolrich ,  James D. Guilford ,  Vinodh Gopal ,  Erdinc Ozturk ,  Sean M. Gulley ,  Wajdi K. Feghali ,  Martin G. Dixon

IPC: G06F9/30 ,  H04L9/06

Abstract: A processor includes a plurality of registers, an instruction decoder to receive an instruction to process a KECCAK state cube of data representing a KECCAK state of a KECCAK hash algorithm, to partition the KECCAK state cube into a plurality of subcubes, and to store the subcubes in the plurality of registers, respectively, and an execution unit coupled to the instruction decoder to perform the KECCAK hash algorithm on the plurality of subcubes respectively stored in the plurality of registers in a vector manner.

公开(公告)号：US10367524B2

公开(公告)日：2019-07-30

申请号：US15496562

申请日：2017-04-25

Applicant: Intel Corporation

Inventor： Gregory B. Tucker ,  James D. Guilford ,  Daniel F. Cutter ,  Vinodh Gopal ,  Wajdi K. Feghali

IPC: G06K9/46 ,  H03M7/40

Abstract: Methods and apparatus are described by which data is compressed using semi-dynamic Huffman code generation. Embodiments generate symbol statistics over a portion of data. The symbol statistics are expanded to include all possible literals that could appear within the data. Any literal or reference added to the statistics may be given a frequency of one. The statistics are used to generate a semi-dynamic Huffman code. The entire data is then compressed using the semi-dynamic Huffman code.

公开(公告)号：US10203934B2

公开(公告)日：2019-02-12

申请号：US13631763

申请日：2012-09-28

Applicant: Intel Corporation

Inventor： Sean M. Gulley ,  Wajdi K. Feghali ,  Vinodh Gopal ,  James D. Guilford ,  Gilbert Wolrich ,  Kirk S. Yap

IPC: G06F5/06 ,  G06F21/64 ,  H04L9/06 ,  H04L9/32

Abstract: Technologies for executing a serial data processing algorithm on a single variable-length data buffer includes padding data segments of the buffer, streaming the data segments into a data register and executing the serial data processing algorithm on each of the segments in parallel.