公开(公告)号：US20230393922A1

公开(公告)日：2023-12-07

申请号：US17965909

申请日：2022-10-14

Applicant: Micron Technology, Inc.

Inventor： Sampath K. Ratnam ,  Sean Brasfield ,  Gary F. Besinga ,  Michael G. Miller ,  Renato C. Padilla ,  Tawalin Opastrakoon

IPC: G06F11/07

CPC classification number: G06F11/0772

Abstract: Respective error handling (EH) flags can be set based at least in part on media management data of a memory device. Whether any of the EH flags are set can be determined. In response to determining that at least one of the EH flags is set, a subset of a plurality of operations of an EH flow associated with the set EH flags can be performed.

公开(公告)号：US11715530B2

公开(公告)日：2023-08-01

申请号：US17837816

申请日：2022-06-10

Applicant: Micron Technology, Inc.

Inventor： Bruce A. Liikanen ,  Gerald L. Cadloni ,  Gary F. Besinga ,  Michael G. Miller ,  Renato C. Padilla

IPC: G11C16/34 ,  G11C29/52 ,  G11C16/26 ,  G11C7/18 ,  G11C8/14 ,  G11C16/04

CPC classification number: G11C16/3404 ,  G11C7/18 ,  G11C8/14 ,  G11C16/0483 ,  G11C16/26 ,  G11C29/52 ,  G11C2207/2254

Abstract: Several embodiments of memory devices and systems with offset memory component automatic calibration error recovery are disclosed herein. In one embodiment, a system includes at least one memory region and calibration circuitry. The memory region has memory cells that read out data states in response to application of a current read level signal. The calibration circuitry is operably coupled to the at least one memory region and is configured to determine a read level offset value corresponding to one or more of a plurality of offset read level test signals, including a base offset read level test signal. The base offset read level test signal is offset from the current read level signal by a predetermined value. The calibration circuitry is further configured to output the determined read level offset value.

公开(公告)号：US20220351796A1

公开(公告)日：2022-11-03

申请号：US17867538

申请日：2022-07-18

Applicant: Micron Technology, Inc.

Inventor： Renato C. Padilla ,  Sampath K. Ratnam ,  Christopher M. Smitchger ,  Vamsi Pavan Rayaprolu ,  Gary F. Besinga ,  Michael G. Miller ,  Tawalin Opastrakoon

IPC: G11C29/10 ,  G06F11/07

Abstract: A method includes associating each block of a plurality of blocks of a memory device with a corresponding frequency access group of a plurality of frequency access groups based on corresponding access frequencies, and performing scan operations on blocks of each of the plurality of frequency access groups using a scan frequency that is different from scan frequencies of other frequency access groups. A scan operation performed on a frequency access group with a higher access frequency uses a higher scan frequency than a scan operation performed on a frequency access group with a lower access frequency.

公开(公告)号：US11456037B2

公开(公告)日：2022-09-27

申请号：US17318603

申请日：2021-05-12

Applicant: Micron Technology, Inc.

Inventor： Harish Singidi ,  Kishore Kumar Muchherla ,  Gianni Stephen Alsasua ,  Ashutosh Malshe ,  Sampath Ratnam ,  Gary F. Besinga ,  Michael G. Miller

IPC: G11C16/26 ,  G11C16/34 ,  G11C11/56 ,  G11C16/08 ,  G11C16/04

Abstract: Disclosed in some examples, are methods, systems, and machine readable mediums which compensate for read-disturb effects by shifting the read voltages used to read the value in a NAND cell based upon a read counter. For example, the NAND memory device may have a read counter that corresponds to a group of NAND cells (e.g., a page, a block, a superblock). Anytime a NAND cell in the group is read, the read counter may be incremented. The read voltage, Vread, may be adjusted based on the read counter to account for the read disturb voltage.

公开(公告)号：US20220276791A1

公开(公告)日：2022-09-01

申请号：US17747548

申请日：2022-05-18

Applicant: Micron Technology, Inc.

Inventor： Michael G. Miller ,  Gary F. Besinga

IPC: G06F3/06

Abstract: An asynchronous power loss (APL) event is detected at a memory device. A last written page is identified in the memory device in response to detecting the APL event. A count of zeros programmed in the last written page is determined. The count of zeros is compared to a threshold constraint to determine whether to perform a dummy write operation on the last written page.

公开(公告)号：US10942796B2

公开(公告)日：2021-03-09

申请号：US16544190

申请日：2019-08-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Michael G. Miller ,  Ashutosh Malshe ,  Violante Moschiano ,  Peter Feeley ,  Gary F. Besinga ,  Sampath K. Ratnam ,  Walter Di-Francesco ,  Renato C. Padilla, Jr. ,  Yun Li ,  Kishore Kumar Muchherla

IPC: G11C11/34 ,  G06F11/07 ,  G06F3/06 ,  G06F11/10 ,  G11C11/56 ,  G11C16/10 ,  G11C16/22 ,  G11C16/30 ,  G11C16/34 ,  G11C5/14

Abstract: Apparatus having an array of memory cells include a controller configured to read a particular memory cell of a last written page of memory cells of a block of memory cells of the array of memory cells, determine whether a threshold voltage of the particular memory cell is less than a particular voltage level, and mark the last written page of memory cells as affected by power loss during a programming operation of the last written page of memory cells when the threshold voltage of the particular memory cell is determined to be higher than the particular voltage level.

公开(公告)号：US10755792B2

公开(公告)日：2020-08-25

申请号：US16448502

申请日：2019-06-21

Applicant: Micron Technology, Inc.

Inventor： Harish Reddy Singidi ,  Kishore Kumar Muchherla ,  Gianni Stephen Alsasua ,  Ashutosh Malshe ,  Sampath Ratnam ,  Gary F. Besinga ,  Michael G. Miller

IPC: G11C16/26 ,  G11C16/34 ,  G11C11/56 ,  G11C16/08 ,  G11C16/04

Abstract: Disclosed in some examples, are methods, systems, and machine readable mediums which compensate for read-disturb effects by shifting the read voltages used to read the value in a NAND cell based upon a read counter. For example, the NAND memory device may have a read counter that corresponds to a group of NAND cells (e.g., a page, a block, a superblock). Anytime a NAND cell in the group is read, the read counter may be incremented. The read voltage, Vread, may be adjusted based on the read counter to account for the read disturb voltage.

公开(公告)号：US20200090767A1

公开(公告)日：2020-03-19

申请号：US16690546

申请日：2019-11-21

Applicant: Micron Technology, Inc.

Inventor： Bruce A. Liikanen ,  Gerald L. Cadloni ,  Gary F. Besinga ,  Michael G. Miller ,  Renato C. Padilla

IPC: G11C16/34 ,  G11C29/52 ,  G11C8/14 ,  G11C16/04 ,  G11C7/18 ,  G11C16/26

Abstract: Several embodiments of memory devices and systems with offset memory component automatic calibration error recovery are disclosed herein. In one embodiment, a system includes at least one memory region and calibration circuitry. The memory region has memory cells that read out data states in response to application of a current read level signal. The calibration circuitry is operably coupled to the at least one memory region and is configured to determine a read level offset value corresponding to one or more of a plurality of offset read level test signals, including a base offset read level test signal. The base offset read level test signal is offset from the current read level signal by a predetermined value. The calibration circuitry is further configured to output the determined read level offset value.

公开(公告)号：US20200027514A1

公开(公告)日：2020-01-23

申请号：US16040382

申请日：2018-07-19

Applicant: Micron Technology, Inc.

Inventor： Michael G. Miller ,  Kishore Kumar Muchherla ,  Harish R. Singidi ,  Walter Di Francesco ,  Renato C. Padilla ,  Gary F. Besinga ,  Violante Moschiano

IPC: G11C16/34 ,  G11C29/50 ,  G11C29/52 ,  G11C16/04 ,  G06F12/02

Abstract: An indication of an initialization of power to a memory component can be received. In response to receiving the indication of the initialization, a last written page of a data block of the memory component can be identified. The last written page is associated with a status indicator. A determination is made of whether the status indicator can be read. Responsive to determining that the status indicator cannot be read, it can be determined that programming of data to the data block of the memory component did not complete based on a prior loss of power to the memory component.

公开(公告)号：US20200004465A1

公开(公告)日：2020-01-02

申请号：US16566545

申请日：2019-09-10

Applicant: Micron Technology, Inc.

Inventor： Michael G. Miller ,  Kishore Kumar Muchherla ,  Harish Reddy Singidi ,  Sampath Ratnam ,  Renato Padilla, JR. ,  Gary F. Besinga ,  Peter Sean Feeley

IPC: G06F3/06 ,  G11C16/10

Abstract: Devices and techniques for correcting for power loss in NAND memory devices are disclosed herein. The NAND memory devices may comprise a number of physical pages. For example, a memory controller may detect a power loss indicator at the NAND flash memory. The memory controller may identify a last-written physical page and determine whether the last-written physical page comprises more than a threshold number of low-read-margin cells. If the last-written physical page comprises more than the threshold number of low-read-margin cells, the memory controller may provide a programming voltage to at least the low-read-margin cells.