公开(公告)号：US20220334961A1

公开(公告)日：2022-10-20

申请号：US17854797

申请日：2022-06-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Mikai Chen ,  Zhenlei Shen ,  Murong Lang ,  Zhenming Zhou

IPC: G06F12/02 ,  G06F11/07 ,  G06F11/30

Abstract: A scaling factor for a data unit of a memory device is obtained. The scaling factor corresponds to a difference between a first error rate associated with a first set of memory access operations performed at the data unit and a second error rate associated with a second set of memory access operations performed at the data unit. A media management operation is scheduled on the data unit in view of the scaling factor.

公开(公告)号：US20220229603A1

公开(公告)日：2022-07-21

申请号：US17716689

申请日：2022-04-08

Applicant: Micron Technology, Inc.

Inventor： Murong Lang ,  Zhenming Zhou

IPC: G06F3/06 ,  G11C7/10 ,  G11C7/22

Abstract: A data structure including a target read voltage level corresponding to each set of values of a plurality of sets of values corresponding to a plurality of operating characteristics is stored. In response to a read command associated with a memory cell, a current set of measured values of the plurality of operating characteristics associated with the memory cell is measured. A match between a first set of values of the plurality of sets of values corresponding to the plurality of operating characteristics and the current set of measured values is identified. Using the data structure, a first stored target read voltage level corresponding to the match between the first set of values and the current set of measured values is identified. The read command is executed using the first stored target read voltage level.

公开(公告)号：US20220115084A1

公开(公告)日：2022-04-14

申请号：US17557782

申请日：2021-12-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Zhongguang Xu ,  Murong Lang ,  Zhenming Zhou

IPC: G11C29/50 ,  G11C29/44 ,  G11C29/12 ,  G11C16/26 ,  G11C16/10

Abstract: A first sequence of operations corresponding to an error recovery process of a memory sub-system is determined. A value corresponding to an operating characteristic of a memory sub-system is determined, the operating characteristic corresponding to execution of a first sequence of operations of an error recovery process. A determination is made that the value satisfies a condition. In response to the value satisfying the first condition, a second sequence of operations corresponding to the error recovery process is executed.

公开(公告)号：US20210132867A1

公开(公告)日：2021-05-06

申请号：US17147126

申请日：2021-01-12

Applicant: Micron Technology, Inc.

Inventor： Murong Lang ,  Zhenming Zhou

IPC: G06F3/06 ,  G11C7/22

Abstract: A data structure is stored that includes a slope value corresponding to each die temperature of a set of die temperatures, where the slope value represents a change of a read voltage level as a function of a delay time of a memory sub-system. Using the data structure, a stored slope value corresponding to a measured die temperature is identified. An adjusted read voltage level is determined based at least in part on the stored slope value. The read command is executed using the adjusted read voltage level.

公开(公告)号：US20210064277A1

公开(公告)日：2021-03-04

申请号：US16552165

申请日：2019-08-27

Applicant: Micron Technology, Inc.

Inventor： Murong Lang ,  Zhenming Zhou

IPC: G06F3/06 ,  G11C7/22 ,  G11C7/10

Abstract: Multiple sets of values corresponding to operating characteristics of a memory sub-system are established. For each of the sets of values, a read voltage level corresponding to a decreased bit error rate of a programming distribution of the memory sub-system is identified. A data structure is stored that includes the read voltage level for each set of values corresponding to the operating characteristics. In response to a read command, a current set of values of the operating characteristics is determined. Using the data structure, a stored read voltage level corresponding to the current set of values of the operating characteristics is identified. The read command is executed using the stored read voltage level corresponding to the current set of values of the operating characteristics.

公开(公告)号：US20210012850A1

公开(公告)日：2021-01-14

申请号：US16510778

申请日：2019-07-12

Applicant: Micron Technology, Inc.

Inventor： Jian Huang ,  Zhenming Zhou

IPC: G11C29/38 ,  G11C29/44

Abstract: A system includes a memory component, and a processing device coupled with the memory component. The processing device to identify a group of management units of the memory component, wherein the group of management units is included in a set of retired groups of management units, select a management unit from the group of management units, perform a media integrity check on the management unit to determine a failed bit count of the management unit, and in response to the failed bit count of the management unit failing to satisfy a threshold criterion, remove the group of management units from the set of retired groups of management units.

公开(公告)号：US10790036B1

公开(公告)日：2020-09-29

申请号：US16553942

申请日：2019-08-28

Applicant: Micron Technology, Inc.

Inventor： Zhenming Zhou ,  Murong Lang

IPC: G11C7/00 ,  G11C16/34 ,  G11C16/26 ,  G11C16/14 ,  G11C16/30 ,  G11C16/10 ,  G11C13/00 ,  G11C29/50

Abstract: A current demarcation voltage is determined, where the current demarcation voltage is to be applied to a memory cell for reading a state of the memory cell. A plurality of test demarcation voltages is determined based on the current demarcation voltage and a space between a first threshold voltage distribution corresponding to a first state of the memory cell and a second threshold voltage distribution corresponding to a second state of the memory cell. For each test demarcation voltage, an error rate of reading the state of the memory cell based on a respective test demarcation voltage is determined. A test demarcation voltage having the lowest error rate from the plurality of test demarcation voltages is determined. The current demarcation voltage is set to correspond to the test demarcation voltage having the lowest error rate.

公开(公告)号：US20250166709A1

公开(公告)日：2025-05-22

申请号：US19023916

申请日：2025-01-16

Applicant: Micron Technology, Inc.

Inventor： Yu-Chung Lien ,  Zhenming Zhou

IPC: G11C16/12 ,  G11C16/10 ,  G11C16/26

Abstract: A method includes determining that a program operation includes a first pass to apply a first voltage distribution to a plurality of memory cells and a second pass to apply a second voltage distribution to the plurality of memory cells, performing the first pass of the program operation using a first sensing time, and performing the second pass of the program operation using a second sensing time during the second pass of the program operation, where the first sensing time is shorter than the second sensing time.

公开(公告)号：US20250140320A1

公开(公告)日：2025-05-01

申请号：US18784434

申请日：2024-07-25

Applicant: Micron Technology, Inc.

Inventor： Hanping Chen ,  Zhongguang Xu ,  Murong Lang ,  Zhenming Zhou

IPC: G11C16/14 ,  G11C16/04 ,  G11C16/26 ,  G11C16/34

Abstract: Apparatuses and methods for performing sensing operations on partially programmed erase blocks are provided. One example apparatus can include a memory array comprising a plurality of erase blocks and a controller coupled to the memory array. The controller can be configured to apply a first sensing voltage to a first access line of a first group of access lines corresponding to the first erase block during a first sensing operation on the first erase block that is partially programmed, apply a first pass voltage to a number of programmed access lines of the first group of access lines corresponding to the first erase block during the first sensing operation, and apply a second pass voltage a number of unprogrammed access lines of the first group of access lines corresponding to the first erase block during the first sensing operation.

公开(公告)号：US20250054549A1

公开(公告)日：2025-02-13

申请号：US18756573

申请日：2024-06-27

Applicant: Micron Technology, Inc.

Inventor： Nagendra Prasad Ganesh Rao ,  Paing Htet ,  Zhenming Zhou

IPC: G11C16/10 ,  G11C16/08 ,  G11C16/26

Abstract: Apparatuses and methods for programming partially programmed blocks with padding are provided. One example apparatus can include a controller configured to program a first number of word lines in a block of word lines in the array of memory cells, wherein the first number of word lines is less that a total number of word lines in the block, and program a second number of word lines of the array of memory cells, wherein the second number of word lines are programmed with padding and wherein the second number of word lines are different word lines that the first number of word lines and the total number of word lines in the block includes the first and second number of word lines.