公开(公告)号：US20240428865A1

公开(公告)日：2024-12-26

申请号：US18745615

申请日：2024-06-17

Applicant: Micron Technology, Inc.

Inventor： Hanping Chen ,  Zhongguang Xu

IPC: G11C16/26 ,  G11C16/08 ,  G11C16/24

Abstract: Apparatuses and methods for determining performing read operations on a partially programmed block are provided. One example apparatus can include a controller configured to apply a read voltage to a first word line in the array of memory cells during a read operation on the first word line, and apply a bit line bias to a number of bit lines coupled to the first word line during the read operation on the first word line, wherein the bit line bias includes a bit line bias offset associated with performing the read operation on a partially programmed block.

公开(公告)号：US20240319886A1

公开(公告)日：2024-09-26

申请号：US18421893

申请日：2024-01-24

Applicant: Micron Technology, Inc.

Inventor： Peng Zhang ,  Lei Lin ,  Hanping Chen ,  Li-Te Chang ,  Zhengang Chen ,  Murong Lang ,  Zhenming Zhou

IPC: G06F3/06

CPC classification number: G06F3/0614 ,  G06F3/0652 ,  G06F3/0679

Abstract: A method for receiving a request for performing a programming operation on one or more memory blocks of a memory device, identifying a value of a media endurance metric associated with the one or more memory blocks, determining a programming voltage offset corresponding to the value of the media endurance metric, and performing, using the programming voltage offset, the programming operation on the one or more memory blocks. The method further includes identifying a program-verify voltage level associated with the one or more memory blocks, determining a program-verify voltage offset associated with the program-verify voltage level and the value of the media endurance metric, and performing, using the program-verify voltage level and the program-verify voltage offset, a program-verify operation on the one or more memory blocks.

公开(公告)号：US20250140320A1

公开(公告)日：2025-05-01

申请号：US18784434

申请日：2024-07-25

Applicant: Micron Technology, Inc.

Inventor： Hanping Chen ,  Zhongguang Xu ,  Murong Lang ,  Zhenming Zhou

IPC: G11C16/14 ,  G11C16/04 ,  G11C16/26 ,  G11C16/34

Abstract: Apparatuses and methods for performing sensing operations on partially programmed erase blocks are provided. One example apparatus can include a memory array comprising a plurality of erase blocks and a controller coupled to the memory array. The controller can be configured to apply a first sensing voltage to a first access line of a first group of access lines corresponding to the first erase block during a first sensing operation on the first erase block that is partially programmed, apply a first pass voltage to a number of programmed access lines of the first group of access lines corresponding to the first erase block during the first sensing operation, and apply a second pass voltage a number of unprogrammed access lines of the first group of access lines corresponding to the first erase block during the first sensing operation.

公开(公告)号：US20250140325A1

公开(公告)日：2025-05-01

申请号：US18784315

申请日：2024-07-25

Applicant: Micron Technology, Inc.

Inventor： Hanping Chen ,  Zhongguang Xu

IPC: G11C16/26 ,  G11C16/08 ,  G11C16/34

Abstract: Apparatuses and methods for performing read operations on partially programmed blocks are provided. One example apparatus can include a controller configured to apply a read voltage to the first inner word line in the array of memory cells during a read operation on the first inner word line, apply a first pass voltage to a second inner word line adjacent to the first inner word line and to a third inner word line adjacent to the first inner word line, apply a second pass voltage to a number of unprogrammed word lines in the array of memory cells in response to determining the read request is for data stored on the first inner word line of the partially programmed block, and apply a third pass voltage to a first number of inner word lines of the number of word lines that are nonadjacent to the first inner word line.

公开(公告)号：US20240331784A1

公开(公告)日：2024-10-03

申请号：US18619094

申请日：2024-03-27

Applicant: Micron Technology, Inc.

Inventor： Hanping Chen ,  Zhongguang Xu ,  Christina Papagianni ,  Yu-Chung Lien ,  Zhenming Zhou

IPC: G11C16/34 ,  G11C16/10 ,  G11C29/52

CPC classification number: G11C16/3459 ,  G11C16/102 ,  G11C29/52

Abstract: A defective portion of a block of a memory device is identified. The defective portion of the block is programmed with a pre-programming voltage pattern. The pre-programming voltage pattern is programmed to the defective portion of the block before a programming operation is performed on a non-defective portion of the block. A verification operation is caused to be performed on the defective portion of the block.

公开(公告)号：US20250104789A1

公开(公告)日：2025-03-27

申请号：US18774799

申请日：2024-07-16

Applicant: Micron Technology, Inc.

Inventor： Zhongguang Xu ,  Hanping Chen ,  Peng Zhang ,  Zhenming Zhou

IPC: G11C29/12

Abstract: A processing device in a memory sub-system performs a first data integrity scan on a block of a memory device to determine a first combined reliability statistic of memory cells in the block associated with a first program level and a second program level, and performs, using a predetermined read level offset corresponding to one of the first program level or the second program level, a second data integrity scan on the block of the memory device to determine a second combined reliability statistic of the memory cells in the block associated with the first program level and the second program level. The processing device determines a difference between the first combined reliability statistic and the second combined reliability statistic and, responsive to the difference between the first combined reliability statistic and the second combined reliability statistic satisfying a threshold criterion, performs a corrective action on the block of the memory device.