公开(公告)号：US20170133148A1

公开(公告)日：2017-05-11

申请号：US15345312

申请日：2016-11-07

Applicant: QUALCOMM Incorporated

Inventor： Mario Francisco VELEZ ,  Niranjan Sunil MUDAKATTE ,  Changhan Hobie YUN ,  Daeik Daniel KIM ,  David Francis BERDY ,  Jonghae KIM ,  Yunfei MA ,  Chengjie ZUO

IPC: H01F27/28 ,  H01L23/00 ,  H01L21/56 ,  H01F38/14 ,  H01F27/02 ,  H01F27/29 ,  H01F41/06 ,  H01L23/31 ,  H04B5/00

CPC classification number: H01F27/2823 ,  H01F27/022 ,  H01F27/2828 ,  H01F27/29 ,  H01F38/14 ,  H01F41/06 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3157 ,  H01L23/5227 ,  H01L23/645 ,  H01L24/06 ,  H01L24/16 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/16 ,  H01L28/00 ,  H01L28/10 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/08265 ,  H01L2224/16227 ,  H01L2224/45015 ,  H01L2224/45147 ,  H01L2224/4813 ,  H01L2224/73257 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/16235 ,  H01L2924/19042 ,  H01L2924/19104 ,  H04B5/0037 ,  H04B5/0081 ,  H01L2224/05599 ,  H01L2924/20751 ,  H01L2224/85399

Abstract: An inductor with multiple loops and semiconductor devices with such an inductor integrated thereon are proposed. In an aspect, the semiconductor device may include a die on a substrate, an inductor on the die in which the inductor comprises a wire with multiple non-planar loops above the die. In another aspect, the semiconductor device may include a plurality of posts on a die on a substrate, and an inductor on the die. The inductor may include a wire looped around the plurality of posts such that the inductor includes multiple non-planar loops.

公开(公告)号：US20170084565A1

公开(公告)日：2017-03-23

申请号：US14859323

申请日：2015-09-20

Applicant: QUALCOMM Incorporated

Inventor： Mario Francisco VELEZ ,  David Francis BERDY ,  Changhan Hobie YUN ,  Jonghae KIM ,  Chengjie ZUO ,  Daeik Daniel KIM ,  Je-Hsiung Jeffrey LAN ,  Niranjan Sunil MUDAKATTE ,  Robert Paul MIKULKA

IPC: H01L23/00

CPC classification number: H01L24/17 ,  H01L23/13 ,  H01L23/49816 ,  H01L24/03 ,  H01L24/09 ,  H01L24/11 ,  H01L2224/023 ,  H01L2224/0905

Abstract: An integrated circuit device in a wafer level package (WLP) includes ball grid array (BGA) balls fabricated with cavities filled with adhesives for improved solder joint reliability.

公开(公告)号：US20170077214A1

公开(公告)日：2017-03-16

申请号：US14853967

申请日：2015-09-14

Applicant: QUALCOMM Incorporated

Inventor： Niranjan Sunil MUDAKATTE ,  Daeik Daniel KIM ,  David Francis BERDY ,  Changhan Hobie YUN ,  Je-Hsiung Jeffrey LAN ,  Chengjie ZUO ,  Mario Francisco VELEZ ,  Robert Paul MIKULKA ,  Jonghae KIM

IPC: H01L49/02

CPC classification number: H01L28/60 ,  H01L23/5223 ,  H01L24/13 ,  H01L27/0805 ,  H01L28/87 ,  H01L28/91 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/13109 ,  H01L2224/94 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/10337 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2224/03

Abstract: An augmented capacitor structure includes a substrate and a first capacitor plate of a first conductive layer on the substrate. The augmented capacitor structure also includes an insulator layer on a surface of the first capacitor plate facing away from the substrate and a second capacitor plate. The second capacitor plate includes a second conductive layer on the insulator layer, supported by the first capacitor plate as a first capacitor. A second capacitor electrically is coupled in series with the first capacitor. The first capacitor plate is shared by the first capacitor and the second capacitor as a shared first capacitor plate. An extended first capacitor plate includes a first dummy portion of a third conductive layer and a first dummy via bar extending along the surface of the shared first capacitor plate. The first dummy portion extends along and is supported by the first dummy via bar.

Abstract translation: 增强电容器结构包括基板和在基板上的第一导电层的第一电容器板。 增强电容器结构还包括在第一电容器板的远离衬底的表面上的绝缘体层和第二电容器板。 第二电容器板包括在绝缘体层上的第二导电层，由第一电容器板作为第一电容器支撑。 与第一电容器串联耦合的第二电容器。 第一电容器板由第一电容器和第二电容器共享作为共用的第一电容器板。 扩展的第一电容器板包括第三导电层的第一虚拟部分和沿着共享的第一电容器板的表面延伸的第一虚设通孔条。 第一虚拟部分沿第一虚拟通孔条延伸并由第一虚拟通孔支撑。

公开(公告)号：US20160254237A1

公开(公告)日：2016-09-01

申请号：US14634148

申请日：2015-02-27

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel KIM ,  David Francis BERDY ,  Mario Francisco VELEZ ,  Changhan Hobie YUN ,  Chengjie ZUO ,  Jonghae KIM ,  Matthew Michael NOWAK

IPC: H01L23/60 ,  H01L21/56 ,  H01L25/065

CPC classification number: H01L23/60 ,  H01L21/568 ,  H01L23/538 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/00 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/0655 ,  H01L2224/04105

Abstract: Ground shielding is achieved by a conductor shield having conductive surfaces that immediately surround individual chips within a fan-out wafer level package (FOWLP) module or device. Intra-module shielding between individual chips within the FOWLP module or device is achieved by electromagnetic or radio-signal (RF) isolation provided by the surfaces of the conductor shield immediately surrounding each of the chips. The conductor shield is directly connected to one or more grounded conductor portions of a FOWLP to ensure reliable grounding.

Abstract translation: 接地屏蔽通过具有导电表面的导体屏蔽来实现，该导电屏蔽立即围绕扇出晶片级封装（FOWLP）模块或器件中的各个芯片。 FOWLP模块或设备内各个芯片之间的模块内屏蔽是通过电磁或无线电信号（RF）隔离来实现的，该隔离由导体屏蔽的表面立即围绕每个芯片。 导体屏蔽层直接连接到FOWLP的一个或多个接地导体部分，以确保可靠的接地。

公开(公告)号：US20150371751A1

公开(公告)日：2015-12-24

申请号：US14313241

申请日：2014-06-24

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel KIM ,  Changhan Hobie YUN ,  Mario Francisco VELEZ ,  Chengjie ZUO ,  David Francis BERDY ,  Jonghae KIM

IPC: H01F27/28 ,  H01F41/04

CPC classification number: H01F27/2804 ,  H01F17/0013 ,  H01F41/04 ,  H01F2017/002 ,  H01F2017/0073 ,  H01F2017/0086 ,  H01L23/15 ,  H01L23/645 ,  H01L28/10 ,  H01L2924/0002 ,  Y10T29/49075 ,  H01L2924/00

Abstract: Methods and apparatuses, wherein the method forms a first plurality of vias in a substrate, further comprising forming the first plurality of vias to be substantially the same height. The method forms a plurality of conductive traces external to the substrate and couples the plurality of conductive traces to the first plurality of vias: wherein the plurality of conductive traces and the first plurality of vias comprise a plurality of conductive turns and wherein the plurality of conductive turns are in a spiral configuration substantially within a first plane.

Abstract translation: 方法和装置，其中所述方法在基底中形成第一多个通孔，还包括将所述第一多个通孔形成为基本上相同的高度。 该方法在衬底外部形成多个导电迹线，并将多个导电迹线耦合到第一多个通孔：其中多个导电迹线和第一多个通孔包括多个导电匝，并且其中多个导电 匝在基本上在第一平面内的螺旋构造。

公开(公告)号：US20150271920A1

公开(公告)日：2015-09-24

申请号：US14220913

申请日：2014-03-20

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel KIM ,  Jonghae KIM ,  Chengjie ZUO ,  Changhan Hobie YUN ,  Mario Francisco VELEZ ,  Robert Paul MIKULKA

IPC: H05K1/11 ,  H05K3/40 ,  H05K3/30 ,  H05K1/03 ,  H05K1/18

CPC classification number: H05K3/303 ,  H01L23/48 ,  H01L23/5385 ,  H01L23/645 ,  H01L2924/0002 ,  H01L2924/19101 ,  H05K1/0243 ,  H05K1/0306 ,  H05K1/111 ,  H05K1/141 ,  H05K1/144 ,  H05K1/165 ,  H05K1/18 ,  H05K3/3436 ,  H05K3/368 ,  H05K3/4007 ,  H05K3/4015 ,  H05K2201/1003 ,  H05K2201/10477 ,  H05K2201/10719 ,  H05K2201/10734 ,  H05K2201/10977 ,  H05K2203/041 ,  H05K2203/1316 ,  Y10T29/4902 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49146 ,  H01L2924/00

Abstract: Systems and methods relate to a semiconductor package comprising a first substrate or a 2D passive-on-glass (POG) structure with a passive component and a first set of one or more package pads formed on a face of a glass substrate. The semiconductor package also includes a second or laminate substrate with a second set of one or more package pads formed on a face of the second or laminate substrate. Solder balls are dropped, configured to contact the first set of one or more package pads with the second set of one or more package pads, wherein the first substrate or the 2D POG structure is placed face-up on the face of the second or laminate substrate. A printed circuit board (PCB) can be coupled to a bottom side of the second or laminate substrate.

Abstract translation: 系统和方法涉及包括第一衬底或2D无源玻璃（POG）结构的半导体封装，其具有无源部件和形成在玻璃衬底的表面上的一个或多个封装焊盘的第一组。 半导体封装还包括具有第二组一个或多个封装焊盘的第二或层压衬底，其形成在第二层压衬底的表面上。 焊球被落下，被配置为使第一组一个或多个封装焊盘与第二组一个或多个封装焊盘接触，其中第一基板或2D POG结构朝上放置在第二或层压板的表面上 基质。 印刷电路板（PCB）可以耦合到第二或层压基板的底侧。

公开(公告)号：US20150201495A1

公开(公告)日：2015-07-16

申请号：US14155187

申请日：2014-01-14

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel KIM ,  Mario Francisco VELEZ ,  Chengjie ZUO ,  Changhan Hobie YUN ,  Jonghae KIM ,  Matthew Michael NOWAK

IPC: H05K1/14 ,  H05K3/06 ,  H05K1/18

CPC classification number: H05K1/141 ,  H01F17/0006 ,  H01F2017/0086 ,  H01L23/49833 ,  H01L28/10 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/15311 ,  H05K1/0306 ,  H05K1/113 ,  H05K1/144 ,  H05K1/181 ,  H05K2201/042 ,  H05K2201/1003 ,  Y10T29/4902 ,  H01L2924/00

Abstract: An integrated circuit device includes a first substrate supporting a pair of conductive interconnects, for example pillars. The device also includes a second substrate on the pair of conductive interconnects. The pair of conductive interconnects is arranged to operate as a first 3D solenoid inductor. The device further includes a conductive trace coupling the pair of conductive interconnects to each other.

Abstract translation: 集成电路装置包括支撑一对导电互连（例如柱）的第一基板。 该装置还包括一对导电互连上的第二基板。 一对导电互连件布置成作为第一3D螺线管电感器工作。 该装置还包括将一对导电互连件彼此耦合的导电迹线。

公开(公告)号：US20150118819A1

公开(公告)日：2015-04-30

申请号：US14554718

申请日：2014-11-26

Applicant: QUALCOMM Incorporated

Inventor： Changhan Hobie YUN ,  Chengjie ZUO ,  Chi Shun LO ,  Jonghae KIM ,  Mario Francisco VELEZ

IPC: H01L29/66

CPC classification number: H01L29/66174 ,  H01G4/1272 ,  H01G4/33 ,  H01L28/40 ,  H01L28/75

Abstract: Methods and apparatus for metal semiconductor wafer bonding for high-Q devices are provided. An exemplary capacitor includes a first plate formed on a glass substrate, a second plate, and a dielectric layer. No organic bonding agent is used between the first plate and the glass substrate, and the dielectric layer can be an intrinsic semiconductor. A extrinsic semiconductor layer that is heavily doped contacts the dielectric layer. The dielectric and extrinsic semiconductor layers are sandwiched between the first and second plates. An intermetallic layer is formed between the first plate and the dielectric layer. The intermetallic layer is thermo compression bonded to the first plate and the dielectric layer. The capacitor can be coupled in a circuit as a high-Q capacitor and/or a varactor, and can be integrated with a mobile device.

Abstract translation: 提供了用于高Q装置的金属半导体晶片接合的方法和装置。 示例性电容器包括形成在玻璃基板，第二板和介电层上的第一板。 在第一板和玻璃基板之间不使用有机粘合剂，并且电介质层可以是本征半导体。 重掺杂的非本征半导体层接触电介质层。 电介质和非本征半导体层夹在第一和第二板之间。 在第一板和电介质层之间形成金属间层。 金属间化合物层被热压接合到第一板和电介质层。 电容器可以作为高Q电容器和/或变容二极管耦合在电路中，并且可以与移动设备集成。

公开(公告)号：US20150014812A1

公开(公告)日：2015-01-15

申请号：US14149530

申请日：2014-01-07

Applicant: QUALCOMM Incorporated

Inventor： Je-Hsiung LAN ,  Chengjie ZUO ,  Changhan Hobie YUN ,  Jonghae KIM ,  Daeik Daniel KIM ,  Mario Francisco VELEZ ,  Robert Paul MIKULKA ,  Niranjan Sunil MUDAKATTE

IPC: H01L49/02

CPC classification number: H01L23/49822 ,  H01L23/5222 ,  H01L23/5227 ,  H01L23/642 ,  H01L23/645 ,  H01L27/016 ,  H01L27/0805 ,  H01L28/10 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit device includes a substrate, and a first interlayer dielectric layer on the substrate that includes a first conductive layer and a second conductive layer. The integrated circuit device also includes a first conductive stack including a third conductive layer coupled to a portion of the second conductive layer with a first via. The integrated circuit device further includes a second conductive stack comprising a fourth conductive layer directly on a portion of the third conductive layer that is isolated from the substrate. The integrated circuit device also includes a second interlayer dielectric layer surrounding the third conductive layer and the fourth conductive layer.

Abstract translation: 集成电路器件包括衬底，以及在衬底上的包括第一导电层和第二导电层的第一层间电介质层。 集成电路器件还包括第一导电叠层，其包括用第一通孔耦合到第二导电层的一部分的第三导电层。 集成电路器件还包括第二导电叠层，其包括直接位于与衬底隔离的第三导电层的一部分上的第四导电层。 集成电路器件还包括围绕第三导电层和第四导电层的第二层间介质层。