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    IMAGING DEVICE AND ELECTRONIC DEVICE
    42.
    发明申请
    IMAGING DEVICE AND ELECTRONIC DEVICE 有权
    成像装置和电子装置

    公开(公告)号：US20160064443A1

    公开(公告)日：2016-03-03

    申请号：US14837040

    申请日：2015-08-27

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Hiroki INOUE ,  Yoshiyuki KUROKAWA ,  Takayuki IKEDA ,  Yuki OKAMOTO

    IPC: H01L27/146 ,  H01L29/24 ,  H01L29/786

    CPC classification number: H01L27/14612 ,  H01L27/14632 ,  H01L27/14643 ,  H01L29/7869

    Abstract: An imaging device capable of obtaining high-quality imaging data is provided. The imaging device includes a first circuit and a second circuit. The first circuit includes a photoelectric conversion element, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a first capacitor, a second capacitor, and a third capacitor. The second circuit includes an eighth transistor. Variation in threshold voltage of an amplifier transistor (the fifth transistor) included in the first circuit can be compensated.

    Abstract translation: 提供能够获得高质量成像数据的成像装置。 成像装置包括第一电路和第二电路。 第一电路包括光电转换元件，第一晶体管，第二晶体管，第三晶体管，第四晶体管，第五晶体管，第六晶体管，第七晶体管，第一电容器，第二电容器和第三电容器。 第二电路包括第八晶体管。 可以补偿包括在第一电路中的放大器晶体管（第五晶体管）的阈值电压的变化。

    SEMICONDUCTOR DEVICE
    43.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20160064383A1

    公开(公告)日：2016-03-03

    申请号：US14935607

    申请日：2015-11-09

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Kiyoshi KATO ,  Shuhei NAGATSUKA ,  Hiroki INOUE ,  Takanori MATSUZAKI

    IPC: H01L27/108

    CPC classification number: H01L27/108 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/1156 ,  H01L27/1225

    Abstract: A semiconductor device with a novel structure in which stored data can be held even when power is not supplied and there is no limitation on the number of times of writing. In the semiconductor device, a plurality of memory cells each including a first transistor, a second transistor, and a capacitor is provided in matrix and a wiring (also called a bit line) for connecting one memory cell to another memory cell and a source or drain electrode of the first transistor are electrically connected to each other through a source or drain electrode of the second transistor. Accordingly, the number of wirings can be smaller than that in the case where the source or drain electrode of the first transistor and the source or drain electrode of the second transistor are connected to different wirings. Thus, the degree of integration of the semiconductor device can be increased.

    Abstract translation: 具有新颖结构的半导体器件，其中即使在不提供电力的情况下也可以保持存储的数据，并且对写入次数没有限制。 在半导体装置中，以矩阵形式设置有各自包括第一晶体管，第二晶体管和电容器的多个存储单元，以及用于将一个存储单元连接到另一个存储单元的源（或称为位线） 第一晶体管的漏极电极通过第二晶体管的源极或漏极电极彼此电连接。 因此，布线数量可以比第一晶体管的源极或漏极以及第二晶体管的源极或漏极连接到不同的布线的情况下的布线数量小。 因此，可以提高半导体器件的集成度。

    SEMICONDUCTOR DEVICE
    45.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20240396105A1

    公开(公告)日：2024-11-28

    申请号：US18676728

    申请日：2024-05-29

    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    Inventor： Ryota TAJIMA ,  Kei TAKAHASHI ,  Hiroki INOUE ,  Munehiro KOZUMA ,  Takahiro FUKUTOME

    IPC: H01M10/44 ,  G01R31/367 ,  H01M10/48 ,  H02J7/00

    Abstract: A semiconductor device that inhibits deterioration of a secondary battery is provided. The semiconductor device includes a secondary battery module and a first circuit. The secondary battery module includes a secondary battery and a sensor. The first circuit includes a variable resistor. The sensor has a function of measuring a temperature of the secondary battery. The first circuit has a function of judging the charge voltage of the secondary battery and outputting a first result; a function of judging the temperature of the secondary battery measured by the sensor and outputting a second result; a function of determining the magnitude of the variable resistor on the basis of the first result and the second result; a function of discharging the charge voltage through the variable resistor; and a function of stopping discharge when the charge voltage reaches a specified voltage.

    LOGIC CIRCUIT FORMED USING UNIPOLAR TRANSISTOR, AND SEMICONDUCTOR DEVICE
    46.
    发明公开
    LOGIC CIRCUIT FORMED USING UNIPOLAR TRANSISTOR, AND SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240364343A1

    公开(公告)日：2024-10-31

    申请号：US18766726

    申请日：2024-07-09

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Hiroki INOUE ,  Munehiro KOZUMA ,  Takeshi AOKI ,  Shuji FUKAI ,  Fumika AKASAWA ,  Shintaro HARADA ,  Sho NAGAO

    IPC: H03K19/094 ,  H01L27/06

    CPC classification number: H03K19/094 ,  H01L27/0629

    Abstract: A semiconductor device using unipolar transistors, in which high and low levels are expressed using high and low power supply potentials, is provided. The semiconductor device includes four transistors, two capacitors, two wirings, two input terminals, and an output terminal. A source or a drain of the first transistor and a source or a drain of the fourth transistor are electrically connected to the first wiring. A gate of the fourth transistor is electrically connected to the first input terminal, and a gate of the second transistor is electrically connected to the second input terminal. A source or a drain of the second transistor and a source or a drain of the third transistor are electrically connected to the second wiring. The first transistor, the second transistor, and the two capacitors are electrically connected to the output terminal.

    MEMORY DEVICE
    47.
    发明公开
    MEMORY DEVICE 审中-公开

    公开(公告)号：US20240147687A1

    公开(公告)日：2024-05-02

    申请号：US18382075

    申请日：2023-10-20

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Takanori MATSUZAKI ,  Hiroki INOUE ,  Yuki OKAMOTO

    IPC: H10B12/00

    CPC classification number: H10B12/00

    Abstract: A memory device that can be highly integrated is provided. The memory device includes a first transistor and a second transistor in a memory cell, and small-area vertical transistors each including a channel formation region on a side surface of an opening portion provided in an insulating layer are used as the two transistors. The memory cell includes a conductor having a function of a gate electrode of the first transistor and a function of one of a source electrode and a drain electrode of the second transistor. The memory cells are placed in a staggered arrangement, so that the memory device can be highly integrated.

    IMAGING DEVICE, OPERATION METHOD THEREOF, AND ELECTRONIC DEVICE
    49.
    发明公开
    IMAGING DEVICE, OPERATION METHOD THEREOF, AND ELECTRONIC DEVICE 审中-公开

    公开(公告)号：US20230247331A1

    公开(公告)日：2023-08-03

    申请号：US17768972

    申请日：2020-10-27

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Seiichi YONEDA ,  Hiroki INOUE

    IPC: H04N25/78 ,  H04N25/709 ,  H04N25/77

    CPC classification number: H04N25/78 ,  H04N25/709 ,  H04N25/77 ,  H10K39/32

    Abstract: An imaging device with low power consumption is provided. A pixel includes a first circuit and a second circuit. The first circuit can generate imaging data and retain difference data that is a difference between the imaging data and data obtained in an initial frame. The second circuit includes a circuit that compares the difference data and a voltage range set arbitrarily. The second circuit supplies a reading signal based on the comparison result. With the use of the structure, reading from the pixel is not performed when it is determined that the difference data is within the set voltage range and reading from the pixel can be performed when it is determined that the difference data is outside the voltage range.

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