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公开(公告)号：US20220060199A1
公开(公告)日：2022-02-24
申请号：US16999250
申请日：2020-08-21
Applicant: Seagate Technology LLC
Inventor： Zheng Wang , Marcus Marrow , Jason Bellorado
Abstract: In a one-shot state transition encoder, L-bits of user data are received and encoded into a codeword of N-bits, wherein N>L. The encoding of the user data involves repeatedly performing: a) encoding a portion of user bits from the user data to a portion of encoded bits of the codeword based on a set of state transition probabilities, thereby reducing a size of a remaining buffer of the codeword and reducing a number of unencoded bits of the user data; and b) based on the number of unencoded bits of the user data being greater than or equal to the remaining buffer size of the codeword, terminating further encoding and storing the unencoded bits of the user data into the remaining buffer of the codeword.
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公开(公告)号：US20200065262A1
公开(公告)日：2020-02-27
申请号：US16672718
申请日：2019-11-04
Applicant: Seagate Technology LLC
Inventor： Jason Bellorado , Marcus Marrow , Zheng Wu
Abstract: Systems and methods are disclosed for full utilization of a data path's dynamic range. In certain embodiments, an apparatus may comprise a circuit including a first filter to digitally filter and output a first signal, a second filter to digitally filter and output a second signal, a summing node, and a first adaptation circuit. The summing node combine the first signal and the second signal to generate a combined signal at a summing node output. The first adaptation circuit may be configured to receive the combined signal, and filter the first signal and the second signal to set a dynamic amplitude range of the combined signal at the summing node output by modifying a first coefficient of the first filter and a second coefficient of the second filter based on the combined signal.
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公开(公告)号：US10559321B1
公开(公告)日：2020-02-11
申请号：US16274669
申请日：2019-02-13
Applicant: Seagate Technology LLC
Inventor： Zheng Wu , Jason Bellorado , Marcus Marrow , Vincent B Ashe
Abstract: In one implementation, the disclosure provides a system including a first circuit to compute a timing error based on a received error signal and an estimated interference signal and a timing loop filter to output a frequency offset and a phase shift based on the timing error received as input. The system also includes a phase accumulator to accumulate at least a phase shift to generate a sample index and phase and an interpolation filter to generate samples of a side track signal using the sample index and phase.
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公开(公告)号：US10469290B1
公开(公告)日：2019-11-05
申请号：US15800738
申请日：2017-11-01
Applicant: Seagate Technology LLC
Inventor： Marcus Marrow , Jason Bellorado
IPC: H04L25/03
Abstract: An apparatus may include a circuit configured to process at least one input signal using a set of channel parameters. The circuit may adapt, using a regularized adaptation algorithm, a first set of channel parameters for use by the circuit as the set of channel parameters in processing the at least one input signal, the regularized adaptation algorithm penalizing deviations by the first set of channel parameters from a corresponding predetermined second set of channel parameters. The circuit may then perform the processing of the at least one input signal using the first set of channel parameters as the set of channel parameters.
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公开(公告)号：US20180366155A1
公开(公告)日：2018-12-20
申请号：US15791190
申请日：2017-10-23
Applicant: Seagate Technology LLC
Inventor： Jason Bellorado , Marcus Marrow , Zheng Wu
Abstract: An apparatus may include a circuit configured to receive a first phase control value of a phase control value signal, generate a first phase interpolator control signal value of a phase interpolator control signal and generate a first digital interpolator control signal value of a digital interpolator control signal. The apparatus may further be configured to phase interpolate a clock signal based on the first phase interpolator control signal value to produce a phase shifted clock signal and digitally interpolate a digital sample based on the first digital interpolator signal value to produce a phase shifted digital sample having an effective phase based on the first phase control value, the digital sample generated using the phase shifted clock signal as a sample clock.
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Patent Agency Ranking
公开(公告)号：US10157637B1
公开(公告)日：2018-12-18
申请号：US15722641
申请日：2017-10-02
Applicant: Seagate Technology LLC
Inventor： Marcus Marrow , Jason Bellorado , Zheng Wu
Abstract: Systems and methods are disclosed for sampling signals in multi-reader magnetic recording. In certain embodiments, an apparatus may comprise a plurality of read heads configured to simultaneously read from a single track of a storage medium, a plurality of analog to digital converters (ADCs) configured to receive signal patterns from corresponding read heads, and a circuit configured to control the plurality of ADCs to sample the signal patterns according to a single clock signal generator. The output of the ADCs may be individually delayed based on a down-track offset of the read heads in order to align the samples, so that samples corresponding to the same portion of the recorded signal can be combined for bit pattern detection.
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公开(公告)号：US10014026B1
公开(公告)日：2018-07-03
申请号：US15713991
申请日：2017-09-25
Applicant: Seagate Technology LLC
Inventor： Zheng Wu , Marcus Marrow , Jason Bellorado
IPC: G11B20/10
CPC classification number: G11B5/59666 , G11B5/59633 , G11B20/10037 , G11B20/10055 , G11B20/10222 , G11B20/1024 , H03K5/131 , H03K5/135 , H03K2005/00019 , H03L7/07 , H03L7/0814 , H03L7/091 , H03M1/001 , H03M13/2951 , H03M13/4146 , H04B1/71055 , H04L7/0025 , H04L7/0029 , H04L7/0331
Abstract: Systems and methods are disclosed for head delay calibration and tracking multi-sensor magnetic recording (MSMR) systems. In certain embodiments, an apparatus may comprise a first reader and a second reader configured to simultaneously read from a single track of a data storage medium, the first reader offset from the second reader such that the first reader and the second reader detect a same signal pattern offset in time. The apparatus may further comprise a circuit configured to determine a relative offset between the first reader and the second reader, including setting a fixed delay for a first signal from the first reader, setting a second delay for a second signal from the second reader, and adjusting the second delay to align the second signal to the first signal using a timing loop, with the first signal used as a reference signal.
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公开(公告)号：US11762731B2
公开(公告)日：2023-09-19
申请号：US17525443
申请日：2021-11-12
Applicant: Seagate Technology LLC
Inventor： Jason Bellorado , Deepak Sridhara
CPC classification number: G06F11/1004 , H03M13/2909
Abstract: Systems and methods are disclosed for an improved utilization of parity within a data storage device, and manufacturing methods thereof. In some embodiments, a data storage device can implement an improved codeword redundancy process that can be utilized for data storage locations which were not previously scanned for defects. In some embodiments, a data storage device can implement an improved codeword redundancy process to store write data to a data storage location without having to perform a read operation prior to storing the write data to the storage location. The improved codeword redundancy process can include various methods of storing or updating an outer code codeword for the data to be stored.
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公开(公告)号：US20230212666A1
公开(公告)日：2023-07-06
申请号：US17565696
申请日：2021-12-30
Applicant: Seagate Technology LLC
Inventor： Raman Venkataramani , William M. Radich , Jason Bellorado
IPC: C12Q1/6874 , G16B30/10
CPC classification number: C12Q1/6874 , G16B30/10
Abstract: Systems and methods are disclosed for performing segmentation and labeling of signals generated by single molecule sequencing. In certain embodiments, a method may comprise receiving a training signal generated by molecular detection, segmenting the training signal into a set of events, determining signal characteristics for the set of events, generating a Hidden Markov Model (HMM) based on the set of events and the signal characteristics. The HMM may also be applied to a second signal and may responsively segment the second signal into a second set of events and label the second set of events based on the signal characteristics. A labeled sequence signal output may be provided that includes the second set of events and corresponding labels generated by the HMM.
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公开(公告)号：US20230206951A1
公开(公告)日：2023-06-29
申请号：US17562426
申请日：2021-12-27
Applicant: Seagate Technology LLC
Inventor： Zheng Wu , Jason Bellorado
IPC: G11B11/105 , G11B5/596
CPC classification number: G11B11/10578 , G11B5/59655
Abstract: Systems and methods are disclosed for phase locking of a clock. In some embodiments, a phase locked clock (PLC) module can phase-lock a write clock to a media written with multiple servo zones of different frequencies. In some implementations, this can be utilized to perform a self-servo write (SSW) of a disc surface within a hard disc drive (HDD). A PLC module can perform a method of writing with a single frequency phase coherently while a read element passes over servo zones with different frequencies. While the PLC module can perform such methods for a SSW process, the methods can also be utilized for other applications that can benefit from writing with a single frequency phase coherently based on servo zones with different frequencies.
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