公开(公告)号：US11704391B2

公开(公告)日：2023-07-18

申请号：US17487517

申请日：2021-09-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Deepak Kumar Poddar ,  Mihir Mody ,  Veeramanikandan Raju ,  Jason A. T. Jones

IPC: G06F21/00 ,  G06F21/16 ,  G06N20/00 ,  G06F21/12 ,  G06N3/047

CPC classification number: G06F21/16 ,  G06F21/121 ,  G06N3/047 ,  G06N20/00

Abstract: In some examples, a system includes storage storing a machine learning model, wherein the machine learning model comprises a plurality of layers comprising multiple weights. The system also includes a processing unit coupled to the storage and operable to group the weights in each layer into a plurality of partitions; determine a number of least significant bits to be used for watermarking in each of the plurality of partitions; insert one or more watermark bits into the determined least significant bits for each of the plurality of partitions; and scramble one or more of the weight bits to produce watermarked and scrambled weights. The system also includes an output device to provide the watermarked and scrambled weights to another device.

公开(公告)号：US11681598B2

公开(公告)日：2023-06-20

申请号：US17135481

申请日：2020-12-28

Applicant: Texas Instruments Incorporated

Inventor： Rajat Sagar ,  Niraj Nandan ,  Kedar Chitnis ,  Brijesh Jadav ,  Mihir Mody

IPC: G06F11/00 ,  G06F11/30 ,  G06F15/78 ,  G06F11/07

CPC classification number: G06F11/3027 ,  G06F11/0757 ,  G06F11/0772 ,  G06F11/3072 ,  G06F15/7807

Abstract: Methods, apparatus, systems and articles of manufacture for an example event processor are disclosed to retrieve an input event and an input event timestamp corresponding to the input event, generate an output event based on the input event and the input event timestamp, in response to determination that an input event threshold is exceeded within a threshold of time, and an anomaly detector to retrieve the output event, determine whether the output event indicates threat to functional safety of a system on a chip, and in response to determining the output event indicates threat to functional safety of the system on a chip, adapt a process for the system on a chip to preserve functional safety.

公开(公告)号：US11662211B2

公开(公告)日：2023-05-30

申请号：US16983437

申请日：2020-08-03

Applicant: Texas Instruments Incorporated

Inventor： Rahul Gulati ,  Aishwarya Dubey ,  Nainala Vyagrheswarudu ,  Vasant Easwaran ,  Prashant Dinkar Karandikar ,  Mihir Mody

IPC: G01C21/20 ,  G06F11/10

CPC classification number: G01C21/206 ,  G06F11/10 ,  G06F2201/845

Abstract: Information communication circuitry, including a first integrated circuit for coupling to a second integrated circuit in a package on package configuration. The first integrated circuit comprises processing circuitry for communicating information bits, and the information bits comprise data bits and error correction bits, where the error correction bits are for indicating whether data bits are received correctly. The second integrated circuit comprises a memory for receiving and storing at least some of the information bits. The information communication circuitry also includes interfacing circuitry for selectively communicating, along a number of conductors, between the package on package configuration. In a first instance, the interfacing circuitry selectively communicates only data bits along the number of conductors. In a second instance, the interfacing circuitry selectively communicates data bits along a first set of the number of conductors and error correction bits along a second set of the number of conductors.

公开(公告)号：US11615043B2

公开(公告)日：2023-03-28

申请号：US17139970

申请日：2020-12-31

Applicant: Texas Instruments Incorporated

Inventor： Niraj Nandan ,  Rajasekhar Reddy Allu ,  Brian Chae ,  Mihir Mody

IPC: G06F13/28 ,  G06F9/48 ,  G06F13/16 ,  G06F13/40

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed herein to enable data aggregation and pattern adaptation in hardware acceleration subsystems. In some examples, a hardware acceleration subsystem includes a first scheduler, a first hardware accelerator coupled to the first scheduler to process at least a first data element and a second data element, and a first load store engine coupled to the first hardware accelerator, the first load store engine configured to communicate with the first scheduler at a superblock level by sending a done signal to the first scheduler in response to determining that a block count is equal to a first BPR value and aggregate the first data element and the second data element based on the first BPR value to generate a first aggregated data element.

公开(公告)号：US20210005005A1

公开(公告)日：2021-01-07

申请号：US17028389

申请日：2020-09-22

Applicant: Texas Instruments Incorporated

Inventor： Mihir Mody ,  Hemant Hariyani ,  Anand Balagopalakrishnan ,  Jason Jones ,  Ajay Jayaraj ,  Manoj Koul

IPC: G06T15/00 ,  G06T1/20

Abstract: A method and system for dynamically transferring graphical image processing operations from a graphical processing unit (GPU) to a digital signal processor (DSP). The method includes estimating the number of operations needed for the processing a set of image data; determining the operational limits of a GPU and compare with estimated number of operations and if the operational limits are exceeded; transfer the processing operations to the DSP from the GPU. The transfer can include transferring a portion of executable code for performing the processing operations, and generating a replacement code for the GPU. The DSP can then process a portion of the image data before sending it to the GPU for further processing.

公开(公告)号：US10515288B2

公开(公告)日：2019-12-24

申请号：US16386723

申请日：2019-04-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Anish Reghunath ,  Hetul Sanghvi ,  Michael Lachmayr ,  Mihir Mody

IPC: G06K9/46 ,  G06K9/62 ,  G06K9/48

Abstract: Systems and methods for performing Census Transforms that includes an input from an image, with a support window created within the image, and a kernel within the support window. The Census Transform calculations and comparisons are performed within the kernel windows. A new Census Transform is disclosed which always inverts a previously made comparison. This new approach can be demonstrated to be equivalent to, applying the original Census Transform, on a pre-processed input kernel, where the pre-processing step adds a fractional position index to each pixel within the N×N kernel. The fractional positional index ensures that no two pixels are equal to one another, and thereby makes the Original Census algorithm on pre-processed kernel same as the new Census algorithm on original kernel. The hardware design for this new Census Transform kernel allows for an always invert of previous comparison system resulting in reduced hardware and power consumption.

公开(公告)号：US12302007B2

公开(公告)日：2025-05-13

申请号：US18147964

申请日：2022-12-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hrushikesh Garud ,  Rajasekhar Allu ,  Gang Hua ,  Jing-Fei Ren ,  Mayank Mangla ,  Niraj Nandan ,  Mihir Mody ,  Pandy Kalimuthu

IPC: H04N23/76 ,  H04N23/11 ,  H04N23/667 ,  H04N23/81 ,  H04N23/84

Abstract: A system is provided. The system generally includes a first processor configured to receive image input data from a red-green-blue infrared (RGBIR) sensor. The first processor of the system is configured to generate a first intermediate image data from the image input data. The system generally includes a second processor. The second processor of the system is configured to generate a second intermediate image data that includes red-green-blue (RGB) image data from the first intermediate image data, and to generate a third intermediate image data that includes infrared (IR) image data from the first intermediate image data. The system generally includes a third processor. The third processor of the system is configured to process the third intermediate image data. The system generally includes a fourth processor. The fourth processor of the system is configured to process the second image data.

公开(公告)号：US20250130737A1

公开(公告)日：2025-04-24

申请号：US18991960

申请日：2024-12-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriramakrishnan Govindarajan ,  Mihir Mody

IPC: G06F3/06 ,  G06F13/28

Abstract: Various systems and methods are provided. One such system includes first and second inputs of first and second types, respectively; a data controller, including a context mapper coupled to the first and second inputs. The data controller includes a context mapper that provides a processing identifier and a storage identifier to each item of data received from the first and second inputs; and a set of processing components, each coupled to the context mapper, and each associated with a respective processing identifier for processing each item of data having the corresponding processing identifier. The system further includes a memory coupled to the context mapper, the memory having multiple storage locations each associated with a respective storage identifier for storing each item of data having the corresponding storage identifier; and first and second outputs of the first and second types, respectively, coupled to the data controller.

公开(公告)号：US12207002B2

公开(公告)日：2025-01-21

申请号：US18194249

申请日：2023-03-31

Applicant: Texas Instruments Incorporated

Inventor： Niraj Nandan ,  Mihir Mody ,  Rajasekhar Allu ,  Manoj Koul ,  Pandy Kalimuthu ,  David Stoller

IPC: H04N23/81 ,  H04N23/84 ,  H04N23/88

Abstract: In described examples, an integrated circuit includes first, second, third, and fourth image processing blocks, a data selection circuitry, and a pipeline memory. An input of the first image processing block receives raw image data. An input of the second image processing block is coupled to an output of the first image processing block. An input of the third image processing block is coupled to an output of the second image processing block. A first input of the data selection circuitry is coupled to an output of the first image processing block, and a second input of the data selection circuitry is coupled to an output of the second image processing block. A data input of the pipeline memory is coupled to an output of the data selection circuitry, and an output of the pipeline memory is coupled to an input of the fourth image processing block.

公开(公告)号：US12204425B2

公开(公告)日：2025-01-21

申请号：US18243421

申请日：2023-09-07

Applicant: Texas Instruments Incorporated

Inventor： Niraj Nandan ,  Hetul Sanghvi ,  Mihir Mody ,  Gary Cooper ,  Anthony Lell

IPC: G06F11/00 ,  G06F9/48 ,  G06F11/22 ,  G06F11/273 ,  G06F13/16 ,  G06F13/28

Abstract: A system to implement debugging for a multi-threaded processor is provided. The system includes a hardware thread scheduler configured to schedule processing of data, and a plurality of schedulers, each configured to schedule a given pipeline for processing instructions. The system further includes a debug control configured to control at least one of the plurality of schedulers to halt, step, or resume the given pipeline of the at least one of the plurality of schedulers for the data to enable debugging thereof. The system further includes a plurality of hardware accelerators configured to implement a series of tasks in accordance with a schedule provided by a respective scheduler in accordance with a command from the debug control. Each of the plurality of hardware accelerators is coupled to at least one of the plurality of schedulers to execute the instructions for the given pipeline and to a shared memory.